R0E00008AKCE00EP52 Datasheet, PDF (40/43 Pages) Renesas Technology Corp – Microcomputer Development Environment System

E8a Emulator
6. Notes on Using the E8a Emulator
(8) DMAC and DMACII during a user program halt
When the user program is halted or when the memory is referred to or modified during user program execution, DMA
transfer is disabled. In such cases, the E8a emulator sets the registers below as following. Therefore, if you refer to the
registers below in the memory window, etc., it shows that DMA is disabled.
- DMA0 Mode Register (DMD0)
Transfer mode select bit (bit 1, 0)
- DMA1 Mode Register (DMD1)
Transfer mode select bit (bit 1, 0)
- DMA2 Mode Register (DMD2)
Transfer mode select bit (bit 1, 0)
- DMA3 Mode Register (DMD3)
Transfer mode select bit (bit 1, 0)
- Interrupt Control Register
Interrupt request level select bit (bit 2, 1, 0)
- Interrupt Control Register
Interrupt request bit (bit 3)
00: DMA transfer disabled
00: DMA transfer disabled
00: DMA transfer disabled
00: DMA transfer disabled
000: Level 0 (interrupt disabled)
0: Interrupt not requested [*1]
Do not enable DMA transfer from the memory window, etc., but enable it in the user program.
Note
[*1] When restarting the user program, though the E8a emulator sets back the value of a DMA mode register to the
previous value that was set before the program stops, the interrupt request bit remains 0.
REJ10J1877-0201 Rev.2.01 Jun. 26, 2009
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