H8S-2615 Datasheet, PDF (390/479 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

15.1 Register Descriptions
The on-chip clock pulse generator has the following registers.
• System clock control register (SCKCR)
• Low-power control register (LPWRCR)
15.1.1 System Clock Control Register (SCKCR)
SCKCR performs φ clock output control, selection of operation when the PLL circuit frequency
multiplication factor is changed, and medium-speed mode control.
Initial
Bit
Bit Name Value
R/W
Description
7
PSTOP 0
R/W
φ Clock Output Disable
Controls φ output.
High-Speed Mode, Medium-Speed Mode, Subactive
Mode, Sleep Mode, Subsleep Mode
0: φ output
1: Fixed high
Software Standby Mode, Watch Mode, Direct
Transition
0: Fixed high
1: Fixed high
Hardware Standby Mode
0: High impedance
1: High impedance
6 to 4 
All 0

Reserved
These bits are always read as 0.
3
STCS
0
R/W
Frequency Multiplication Factor Switching Mode
Select
Selects the operation when the PLL circuit frequency
multiplication factor is changed.
0: Specified multiplication factor is valid after
transition to software standby mode
1: Specified multiplication factor is valid immediately
after STC1 bit and STC0 bit are rewritten
Rev. 2.00, 05/04, page 356 of 442