H8S-2615 Datasheet, PDF (240/479 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Clocked synchronous mode:
• Data length: 8 bits
• Receive error detection: Overrun errors detected
Smart Card interface:
• Automatic transmission of error signal (parity error) in receive mode
• Error signal detection and automatic data retransmission in transmit mode
• Direct convention and inverse convention both supported
Module data bus
Internal
data bus
RxD
TxD
SCK
RDR
RSR
TDR
TSR
SCMR
SSR
SCR
SMR
BRR
Baud rate
generator
Transmission/
reception control
Parity generation
Clock
Parity check
External clock
Legend:
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
SCMR: Smart card mode register
BRR: Bit rate register
Figure 10.1 Block Diagram of SCI
φ
φ/4
φ/16
φ/64
TEI
TXI
RXI
ERI
Rev. 2.00, 05/04, page 206 of 442