H8S-2615 Datasheet, PDF (106/479 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

5.6 Interrupt Control Modes and Interrupt Operation
The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2.
Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is
selected by SYSCR. Table 5.3 shows the differences between interrupt control mode 0 and
interrupt control mode 2.
Table 5.3 Interrupt Control Modes
Interrupt
Priority Setting
Control Mode Registers
0
Default
2
IPR
Interrupt
Mask Bits Description
I
The priorities of interrupt sources are fixed at
the default settings.
Interrupt sources, except for NMI, are masked
by the I bit.
I2 to I0
8 priority levels other than NMI can be set with
IPR.
8-level interrupt mask control is performed by
bits I2 to I0.
5.6.1 Interrupt Control Mode 0
In interrupt control mode 0, interrupt requests other than for NMI are masked by the I bit of the
CCR in the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held
pending. If the I bit is cleared, an interrupt request is accepted.
3. Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to
the priority system is accepted, and other interrupt requests are held pending.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Rev. 2.00, 05/04, page 72 of 442