H8S-2615 Datasheet, PDF (310/479 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

11.3.5 Transmit Wait Register (TXPR)
TXPR sets a transmit wait after a transmit message is stored in a mailbox (buffer) (CAN bus
arbitration wait).
Initial
Bit Bit Name Value
R/W
Description
15 TXPR7
0
14 TXPR6
0
13 TXPR5
0
12 TXPR4
0
11 TXPR3
0
10 TXPR2
0
9
TXPR1
0
8

0
R/W
These bits set a transmit wait (CAN bus arbitration
R/W
wait) for the corresponding mailboxes 1 to 15. When
TXPRn (n = 1 to 15) is set to 1, the message in
R/W
mailbox n becomes the transmit wait state.
R/W
[Clearing conditions]
R/W
• Completion of message transmission
R/W
• Completion of transmission cancellation
R/W
Bit 8 is reserved. This bit is always read as 0. The
R
write value should always be 0.
7
TXPR15
0
R/W
6
TXPR14
0
R/W
5
TXPR13
0
R/W
4
TXPR12
0
R/W
3
TXPR11
0
R/W
2
TXPR10
0
R/W
1
TXPR9
0
R/W
0
TXPR8
0
R/W
Rev. 2.00, 05/04, page 276 of 442