H8S-2615 Datasheet, PDF (219/479 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

8.8.5 Contention between TCNT Write and Increment Operations
If incrementing occurs in the T₂ state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented.
Figure 8.45 shows the timing in this case.
TCNT write cycle
T₁
T₂
φ
Address
Write signal
TCNT input
clock
TCNT
TCNT address
N
M
TCNT write data
Figure 8.45 Contention between TCNT Write and Increment Operations
8.8.6 Contention between TGR Write and Compare Match
If a compare match occurs in the T₂ state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is prohibited. A compare match does not occur even if the previous
value is written.
Figure 8.46 shows the timing in this case.
Rev. 2.00, 05/04, page 185 of 442