H8S-2615 Datasheet, PDF (221/479 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

8.8.8 Contention between TGR Read and Input Capture
If an input capture signal is generated in the T₁ state of a TGR read cycle, the data that is read will
be that in the buffer after input capture transfer.
Figure 8.48 shows the timing in this case.
φ
Address
Read signal
Input capture
signal
TGR
Internal
data bus
TGR read cycle
T₁
T₂
TGR address
X
M
M
Figure 8.48 Contention between TGR Read and Input Capture
8.8.9 Contention between TGR Write and Input Capture
If an input capture signal is generated in the T₂ state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 8.49 shows the timing in this case.
Rev. 2.00, 05/04, page 187 of 442