H8S-2615 Datasheet, PDF (196/479 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

TCNT_1
clock
TCNT_1
TCNT_2
clock
H'03A1
TCNT_2 H'FFFF
TIOCA1,
TIOCA2
TGRA_1
H'03A2
H'0000
H'03A2
H'0001
TGRA_2
H'0000
Figure 8.18 Example of Cascaded Operation (1)
Figure 8.19 illustrates the operation when TCNT_2 overflow/underflow counting has been set for
TCNT_1 and phase counting mode has been designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKA
TCLKB
TCNT_2
TCNT_1
FFFD FFFE FFFF 0000 0001
0002
0001 0000 FFFF
0000
0001
0000
Figure 8.19 Example of Cascaded Operation (2)
8.4.5 PWM Modes
In PWM mode, PWM waveforms are output from the output pins. The output level can be selected
as 0, 1, or toggle output in response to a compare match of each TGR.
TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty.
Designating TGR compare match as the counter clearing source enables the period to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as described below.
Rev. 2.00, 05/04, page 162 of 442