PD16782A_15 Datasheet, PDF (25/29 Pages) Renesas Technology Corp – SOURCE DRIVER FOR 300/288-OUTPUT TFT-LCD

µPD16782A
Switching Characteristics (TA = −30 to +85°C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 V ± 0.5 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Start pulse propagation delay
tPHL
CL = 20 pF
10
time
tPLH
CL = 20 pF
10
Clock frequency 1
fCLK1
Clock frequency 2
fCLK2
With 3-phase clock input
Logic input capacitance
CI1
Other than STHL, STHR
STHL, STHR input capacitance CI2
STHL, STHR
Video input capacitance
C3
C1 to C3, VVI = 2.0 V
54
ns
54
ns
15
MHz
15
MHz
15
pF
20
pF
50
pF
Timing Requirements (TA = −30 to +85°C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 V ± 0.5 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Clock pulse width
PWCLI
Duty = 50%
33
ns
CLK-CLK time
tCL1-2
tCL2-3
16.6
ns
16.6
ns
tCL3-1
16.6
ns
tCL1-2 + tCL2-3 + tCL3-1
1/fCLI1
ns
Start pulse setup time
tSETUP
8
Start pulse hold time
tHOLD
8
Reset pulse width
PWRES
66
INH setup time
tISETUP
33
INH hold time
tIHOLD
33
Reset-INH time
tR-I
81
INH pulse width
PWINH
CLI1
5
ns
ns
ns
ns
ns
ns
CLK
Remark Keep the rise and fall times of the logic input signals to within tr = tf = 5 ns (10 to 90%).
As an example, the switching characteristic wave of CLI1 is defined on the next page.
Data Sheet S16593EJ1V0DS
23