PD16782A_15 Datasheet, PDF (21/29 Pages) Renesas Technology Corp – SOURCE DRIVER FOR 300/288-OUTPUT TFT-LCD

µPD16782A
5.2 Sample and Hold Circuit
The sample and hold circuit samples and holds the video signals input to C1 ~ C3 selected by the multiplexer circuit
in the timing shown below. Swa1 to Swb2 are reset by the RESET signal and change at the rising and falling edges
of the INH signal.
RESET
Data undifined
undifined
INH
ON
ON
Swa1
Swa2
Swb1
Swb2
5.3 Output Operation Timing
The sampled video signals are output to the LCD panel by output currents IVOL and IVOH via output buffer.
And be sure to input 5 or more CLKs of CLI1 during INH=H period.
The output operation of this IC is controlled by INH signals.
INH = Hi-Z
INH = Connected with internal circuit (switch sample and hold circuit at the falling edge.)
Therefore, inverting VCOM while INH = L causes current flow to the IC output pins, which may result wrong working.
VCOM Inversion should be done during INH = H (Hi-Z) and output operation to the LCD should be done after the VCOM
becomes stable enough.
Be sure to sufficiently evaluate the picture quality.
INH
Output voltage
VCOM
1 Horizontal period 1 Horizontal period
Data Sheet S16593EJ1V0DS
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