PD16782A_15 Datasheet, PDF (14/29 Pages) Renesas Technology Corp – SOURCE DRIVER FOR 300/288-OUTPUT TFT-LCD

µPD16782A
5.1.2 Vertical stripe array mode (sequential sampling) (MP/TH = L, MP/1.5 = H)
Please input the shift clock to CL1, CL2 and CL3 pin.
Refer to 5.1.5 Relation between Shift Clock CLIn and Internal Sampling Pulse SHPn.
Table 5−2. Relation between Video Signals C1 to C3, and Output Pins (during right shift)
Line No.
(number
RESET
INH
of INHs)
S1 (S300)
Sampling
0
H
L
C1 (C3)
1
L
↓
Output
C1 (C3)
2
L
↓
Output
C1 (C3)
3
L
↓
Output
C1 (C3)
:
:
:
:
Remark ( ) indicates the case of left shift.
S2 (S299)
Sampling
C2 (C2)
Output
C2 (C2)
Output
C2 (C2)
Output
C2 (C2)
:
S3 (S298)
Sampling
C3 (C1)
Output
C3 (C1)
Output
C3 (C1)
Output
C3 (C1)
:
S4 (S297)
...
S299 (S2)
Sampling ... Sampling
C1 (C3)
C2 (C2)
Output ... Output
C1 (C3)
C2 (C2)
Output ... Output
C1 (C3)
C2 (C2)
Output ... Output
C1 (C3)
C2 (C2)
:
...
:
S300 (S1)
Sampling
C3 (C1)
Output
C3 (C1)
Output
C3 (C1)
Output
C3 (C1)
:
Figure 5−3. Pixel Arrangement of Vertical Stripe Array and Multiplexer Operation
R C1
B C2 _µPD16782A
G C3
S1
S2
Right shift (R,/L = "H"), MP/TH = "L", MP/1.5 = "H"
S3
S4
S5
S6
S7
R
B
G
R
B
G
R
R
B
G
R
B
G
R
R
B
G
R
B
G
R
R
B
G
R
B
G
R
R
B
G
R
B
G
R
12
Data Sheet S16593EJ1V0DS