PD16782A_15 Datasheet, PDF (11/29 Pages) Renesas Technology Corp – SOURCE DRIVER FOR 300/288-OUTPUT TFT-LCD

µPD16782A
★ 4. PIN FUNCTIONS
Symbol
C1 to C3
S1 to S300
Pin Name
Video signal
Video signal
STHR,
STHL
Cascade
CLI1 to
CLI3
Shift clock
INH
Inhibit
RESET Reset
MP/TH
MP/1.5
Multiplexer
circuit select
(1)
Multiplexer
circuit select
(2)
Pad No.
30, 47
130 to 429
81 to 86,
48 to 53
69 to 77
66 to 68
63 to 65
54 to 56
I/O
Input
Output
I/O
Input
Input
Input
Input
Description
Input R, G, and B video signals.
Video signal output pins. Video signals which are sampled and held, are output to
these pins during horizontal period.
Start pulse I/O pins of sample hold timing.
In the case of right shift, STHR becomes an input pin and STHL becomes an output
pin.
In the case of left shift, STHL becomes an input pin and STHR becomes an output
pin.
A start pulse is read at the rising edge of CLI1. Sampling pulse SHPn is generated
at the rising edge of CLI1 to CLI3 in the sequential sampling mode, and at the rising
edge of CLI1 in the simultaneous sampling mode (for details, refer to 5.1.5
Relation between Shift Clock CLIn and Internal Sampling Pulse SHPn).
At the falling edge of INH, it is done that the change of Multiplexer circuits and the
conversion of 2 sets of Sample and Hold circuits.
Resets the select counter of the multiplexer and the selector circuit of the two
sample and hold circuits during RESET=H. After reset, the multiplexer is turned
OFF, so sure to input one pulse of the INH signal before inputting the video signal.
If the video signal is input without the INH signal, sampling is not executed.
In the combination of MP/TH and MP/1.5, it can support to the following modes.
57 to 59
Input
Mode
Vertical stripe array (Simultaneous sampling)
Vertical stripe array (Sequential sampling)
Mosaic array
Double-side delta array
MP/TH
L
L
H
H
MP/1.5
L
H
L
H
R,/L
Osel
Shift direction
select
Selection of
number of
outputs
switching
RMON1, Monitor
RMON2
Dummy1 to Dummy
Dummy4
VDD1
Logic power
supply
VDD2
Driver power
supply
VSS1
Logic ground
VSS2
Driver ground
TEST
Test
60 to 62
87 to 89
2, 3, 116,
117
1, 118,
129, 430
23 to 29,
90 to 96
4 to 15,
104 to 115
16 to 22,
97 to 103
119 to 128,
431 to 440
78 to 80
Input
Input
−
−
−
−
−
−
−
R,/L = H: Right shift: STHR → S1 → S300 → STHL
R,/L = L: Left shift: STHL → S300 → S1 → STHR
Selects number of outputs.
Osel = L: 288 output mode
Osel = H: 300 output mode
Output pins S145 to S156 are invalid in 288 output mode. When Osel=L, the output
signals of S145 to S156 become same as S157 to S168 (R,/L = H) or S133 to S144
(R,/L = L).
This pin can measure the connection resistance at the time of COG mounting.
RMON1 and RMON2 are each short inside IC.
It does not connect with other pins inside IC.
No dummy pins are connected with other pins inside IC.
3.0 to 5.5 V
5.0 ± 0.5 V
Connect this pin to ground of system.
Connect this pin to ground of system.
Fix this pin to low level.
Data Sheet S16593EJ1V0DS
9