PD16782A_15 Datasheet, PDF (12/29 Pages) Renesas Technology Corp – SOURCE DRIVER FOR 300/288-OUTPUT TFT-LCD

µPD16782A
5. FUNCTIONAL DESCRIPTION
5.1 Multiplexer Circuit
This circuit selects RGB video signals input to the C1 to C3 pins according to the pixel array of the liquid crystal
panel, and outputs the signals to the S1 ~ S300 pins.
Vertical stripe array(Simultaneous sampling/Sequential sampling), double-side delta array (Sequential sampling), or
mosaic array (Sequential sampling) can be selected by using the MP/TH and MP/1.5 pins.
5.1.1 Vertical stripe array mode(Simultaneous sampling) (MP/TH = L, MP/1.5 = L)
In this mode, the relation between video signals C1 to C3, and output pins is as shown below. This mode is used to
drive a panel of vertical stripe array. In this mode, the multiplexer circuit is in the through status.
Please input the shift clock only to CL1 pin, and fix CL2 and CL3 pin to low level.
Refer to 5.1.5 Relation between Shift Clock CLIn and Internal Sampling Pulse SHPn.
Table 5−1. Relation between Video Signals C1 to C3, and Output Pins (during right shift)
Line No.
(number
RESET
INH
of INHs)
S1 (S300)
Sampling
0
H
L
C1 (C3)
1
L
↓
Output
C1 (C3)
2
L
↓
Output
C1 (C3)
3
L
↓
Output
C1 (C3)
:
:
:
:
Remark ( ) indicates the case of left shift.
S2 (S299)
Sampling
C2 (C2)
Output
C2 (C2)
Output
C2 (C2)
Output
C2 (C2)
:
S3 (S298)
Sampling
C3 (C1)
Output
C3 (C1)
Output
C3 (C1)
Output
C3 (C1)
:
S4 (S297)
...
S299 (S2)
Sampling ... Sampling
C1 (C3)
C2 (C2)
Output ... Output
C1 (C3)
C2 (C2)
Output ... Output
C1 (C3)
C2 (C2)
Output ... Output
C1 (C3)
C2 (C2)
:
...
:
S300 (S1)
Sampling
C3 (C1)
Output
C3 (C1)
Output
C3 (C1)
Output
C3 (C1)
:
Figure 5−1. Pixel Arrangement of Vertical Stripe Array and Multiplexer Operation
R C1
B C2 _µPD16782A
G C3
S1
S2
Right shift (R,/L = "H"), MP/TH = "L", MP/1.5 = "L"
S3
S4
S5
S6
S7
R
B
G
R
B
G
R
R
B
G
R
B
G
R
R
B
G
R
B
G
R
R
B
G
R
B
G
R
R
B
G
R
B
G
R
10
Data Sheet S16593EJ1V0DS