PD16782A_15 Datasheet, PDF (22/29 Pages) Renesas Technology Corp – SOURCE DRIVER FOR 300/288-OUTPUT TFT-LCD

µPD16782A
Cautions 1. In order to prevent destruction due to latch-up, keep the power-on sequence [VDD1 Æ logic input
Æ VDD2 Æ video signal input ] and power-off in the reverse sequence. Observe this power
sequence even during the transition period.
2. The µPD16782A is designed to input successive signals such as chrome signals. The input
band of the video signals is designed to be 9 MHz MAX. If video signals faster than that are
input, display is not performed correctly.
3. Insert a bypass capacitor of 0.1 µF between VDD1 and VSS1 and between VDD2 and VSS2. If the
power supply is not reinforced, the sampling voltage may be abnormal if the supply voltage
fluctuates.
4. Even if the start pulse width is extended by half a clock or more, sampling start timing SHP1 is
not affected, and the sampling operation is performed normally.
5. To reset the IC after power-on, the below timing sequence should be kept. (The following timing
charts show simultaneous sampling.)
If RESET signal is input 1 time after power-on , it is not required after that. Besides, please be sure to input
INH signal after RESET signal input.
RESET pulse width: 66 ns MIN.
tR-1: 81 ns MIN.
INH pulse width: 5 CLK MIN. (CLI1 is active)
CLI1
PWRES
12345
123
RESET
tISETUP
tR–I
INH
STHR (STHL)
tIHOLD
PWINH: 5 clocks MIN.
3 clocks MIN.
SHP1 to SHP 3
SHP4 to SHP6
SHP7 to SHP 9
20
Data Sheet S16593EJ1V0DS