HYS72T64300HP-3S-A Datasheet, PDF (7/50 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[64/128]3x0HP–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Pin No.
220
221
192
74
73
18
Name
S2
NC
S3
NC
RAS
CAS
WE
RESET
Address Signals
71
BA0
190
BA1
54
BA2
NC
188
A0
183
A1
63
A2
182
A3
61
A4
60
A5
180
A6
58
A7
179
A8
177
A9
70
A10
AP
57
A11
176
A12
196
A13
NC
Pin Buffer
Type Type
I
SSTL
NC —
I
SSTL
NC —
I
SSTL
I
SSTL
I
SSTL
I
CMOS
Function
Rank 2 is selected by S2
Not Connected
Note: 1-Rank, 2-Ranks module
Rank 3 is selected by S3
Not Connected
Note: 1-Rank, 2-Ranks module
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
When sampled at the cross point of the rising edge of CK, and falling
edge of CK, RAS, CAS and WE define the operation to be executed by
the SDRAM.
Register Reset
The RESET pin is connected to the RST pin on the register and to the
OE pin on the PLL. When LOW, all register outputs will be driven LOW
and the PLL clocks to the DRAMs and the register(s) will be set to low-
level. The PLL will remain synchronized with the input clock.
I
SSTL Bank Address Bus 1:0
I
SSTL ^{Selects internal SDRAM memory bank}
I
SSTL Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
I
SSTL Not Connected
Less than 1Gb DDR2 SDRAMS
I
SSTL Address Bus 12:0, Address Signal 10/AutoPrecharge
I
SSTL ^{During a Bank Activate command cycle, defines the row address when}
sampled at the crosspoint of the rising edge of CK and falling edge of
I
SSTL _{CK. During a Read or Write command cycle, defines the column}
I
SSTL _{address when sampled at the cross point of the rising edge of CK and}
I
SSTL ^{falling edge of CK. In addition to the column address, AP is used to}
I
SSTL ^{invoke autoprecharge operation at the end of the burst read or write}
cycle. If AP is HIGH, autoprecharge is selected and BA[12:0] defines
I
SSTL _{the bank to be precharged. If AP is LOW, autoprecharge is disabled.}
I
SSTL During a Precharge command cycle, AP is used in conjunction with
I
SSTL ^{BA[12:0] to control which bank(s) to precharge. If AP is HIGH, all banks}
I
SSTL
will be precharged regardless of the state of BA[12:0] inputs. If AP is
LOW, then BA[12:0] are used to define which bank to precharge.
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL Address Signal 13
NC —
Not Connected
Note: Non CA parity modules based on 256 Mbit component
Rev. 1.22, 2007-06
7
07042006-834B-Z31V