HYS72T64300HP-3S-A Datasheet, PDF (4/50 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[64/128]3x0HP–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
1.2
Description
The QIMONDA HYS72T[64/128]3x0HP–[3S/3.7/5]–A
module family are Very Low Profile (VLP) Registered DIMM
(RDIMM with parity) with 18.30 mm height based on DDR2
technology. DIMMs are available as ECC modules in
64M x 72 (512 MByte) and 128M x 72 (1 GByte) organization
and density, intended for mounting into 240-Pin connector
sockets.
The memory array is designed with 512-Mbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs. All control and
address signals are re-driven on the DIMM using register
devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to
the SDRAM timing. Decoupling capacitors are mounted on
the PCB board. The DIMMs feature serial presence detect
based on a serial E²PROM device using the 2-pin I²C
protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to
the customer.
Product Type¹⁾
Compliance Code²⁾
TABLE 2
Ordering Information for RoHS Compliant Products
Description SDRAM Technology
PC2–5300
HYS72T64300HP–3S–A
512 MB 1R×8 PC2–5300P–555–12–R0
1 Rank, ECC 512 Mbit (×8)
HYS72T128300HP–3S–A
1 GB 1R×4 PC2–5300P–555–12–U0
1 Rank, ECC 512 Mbit (×4)
HYS72T128320HP–3S–A
1 GB 2R×8 PC2–5300P–555–12–T0
2 Ranks, ECC 512 Mbit (×8)
PC2–4200
HYS72T64300HP–3.7–A
512 MB 1R×8 PC2–4200P–444–12–R0
1 Rank, ECC 512 Mbit (×8)
HYS72T128300HP–3.7–A
1 GB 1R×4 PC2–4200P–444–12–U0
1 Rank, ECC 512 Mbit (×4)
HYS72T128320HP–3.7–A
1 GB 2R×8 PC2–4200P–444–12–T0
2 Ranks, ECC 512 Mbit (×8)
PC2–3200
HYS72T128320HP–5–A
1 GB 2R×8 PC2–3200P–333–12–T0
2 Ranks, ECC 512 Mbit (×8)
1) All part numbers end with a place code, designating the silicon die revision. Example: HYS72T128300HP–3.7–A, indicating Rev. “A” dies
are used for DDR2 SDRAM components. For all QIMONDA DDR2 module and component nomenclature see Chapter 6 of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200P–444–12–R0”, where
4200P means Very Low Profile Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address
Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD
Revision 1.2 and produced on the Raw Card “R”
DIMM
Density
512 MB
1 GB
1 GB
Module
Organization
64M × 72
128M × 72
128M × 72
Memory
Ranks
1
1
2
ECC/
Non-ECC
ECC
ECC
ECC
# of
SDRAMs
9
18
18
TABLE 3
Address Format
# of row/bank/columns bits Raw Card
14/2/10
R
14/2/11
U
14/2/10
T
Rev. 1.22, 2007-06
4
07042006-834B-Z31V