HYS72T64300HP-3S-A Datasheet, PDF (31/50 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[64/128]3x0HP–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol Note
1)2)3)4)5)
Self-Refresh Current
I_DD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING. I_DD6 current values are guaranteed up to T_CASE of 85 °C max.
All Bank Interleave Read Current
I_DD7
6)
All banks are being interleaved at minimum t_RC without violating t_RRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. I_out = 0 mA.
1) V_DDQ = 1.8 V ± 0.1 V; V_DD = 1.8 V ± 0.1 V
2) I_DD specifications are tested after the device is properly initialized and I_DD parameter are specified with ODT disabled.
3) Definitions for I_DD see Table 21
4) For two rank modules: All active current measurements in the same I_DD current mode. The other rank is in I_DD2P Precharge Power-Down
Mode
5) For details and notes see the relevant Qimonda component data sheet
6) I_DD1, I_DD4R and I_DD7 current measurements are defined with the outputs disabled (I_OUT = 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
Parameter
LOW
STABLE
FLOATING
SWITCHING
Description
TABLE 21
Definitions for I_DD
V_IN ≤ V_IL(ac).MAX, HIGH is defined as V_IN ≥ V_IH(ac).MIN
Inputs are stable at a HIGH or LOW level
Inputs are V_REF = V_DDQ /2
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes
Rev. 1.22, 2007-06
32
07042006-834B-Z31V