HYS72T64300HP-3S-A Datasheet, PDF (26/50 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[64/128]3x0HP–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
13) The t_HZ, t_RPST and t_LZ, t_RPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(t_HZ, t_RPST), or begins driving (t_LZ, t_RPRE). t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C≤ T_CASE ≤ 85 °C
16) 85 °C < T_CASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The t_RRD timing parameter depends on the page size of the DRAM organization.
19) The maximum limit for the t_WPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) Minimum t_WTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing t_XARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing t_XARDS has to be satisfied.
22) WR must be programmed to fulfill the minimum requirement for the t_WR timing parameter, where WR_MIN[cycles] = t_WR(ns)/t_CK(ns) rounded
up to the next integer value. t_DAL = WR + (t_RP/t_CK). For each of the terms, if not already an integer, round to the next highest integer. t_CK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
Parameter
TABLE 17
DRAM Component Timing Parameter by Speed Grade - DDR2-400
Symbol
DDR2–400
Min.
Max.
Unit
Notes^1)2)3)4)5)
6)7)
DQ output access time from CK / CK
t_AC
CAS A to CAS B command period
t_CCD
CK, CK high-level width
t_CH
CKE minimum high and low pulse width
t_CKE
CK, CK low-level width
t_CL
Auto-Precharge write recovery + precharge t_DAL
time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
t_DELAY
DQ and DM input hold time (differential data t_DH(base)
strobe)
DQ and DM input hold time (single ended data t_DH1(base)
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
t_DIPW
t_DQSCK
t_DQSL,H
t_DQSQ
Write command to 1st DQS latching transition t_DQSS
DQ and DM input setup time (differential data t_DS(base)
strobe)
DQ and DM input setup time (single ended
data strobe)
t_DS1(base)
DQS falling edge hold time from CK (write
t_DSH
cycle)
–600
2
0.45
3
0.45
WR + t_RP
t_IS + t_CK + t_IH
275
–25
0.35
–500
0.35
—
– 0.25
150
–25
0.2
+600
—
0.55
—
0.55
—
––
––
—
—
+500
—
350
+ 0.25
—
—
—
ps
t_CK
t_CK
t_CK
t_CK
t_CK
8)21)
ns
9)
ps
10)
ps
11)
t_CK
ps
t_CK
ps
11)
t_CK
ps
11)
ps
11)
t_CK
Rev. 1.22, 2007-06
27
07042006-834B-Z31V