HYS72T64300HP-3S-A Datasheet, PDF (21/50 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[64/128]3x0HP–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_ERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_{ERR(6-10PER).MIN} = – 272
ps and t_{ERR(6- 10PER).MAX} = + 293 ps, then t_{DQSCK.MIN(DERATED)} = t_DQSCK.MIN – t_{ERR(6-10PER).MAX} = – 400 ps – 293 ps = – 693 ps and
t_{DQSCK.MAX(DERATED)} = t_DQSCK.MAX – t_{ERR(6-10PER).MIN} = 400 ps + 272 ps = + 672 ps. Similarly, t_LZ.DQ for DDR2–667 derates to t_{LZ.DQ.MIN(DERATED)}
= - 900 ps – 293 ps = – 1193 ps and t_{LZ.DQ.MAX(DERATED)} = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations ).
12) t_CKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of t_IS + 2 x t_CK + t_IH.
13) DAL = WR + RU{t_RP(ns) / t_CK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For t_RP, if the result
of the division is not already an integer, round up to the next highest integer. t_CK refers to the application clock period. Example: For
DDR2–533 at t_CK = 3.75 ns with t_WR programmed to 4 clocks. t_DAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
14) t_DAL.nCK = WR [nCK] + t_nRP.nCK = WR + RU{t_RP [ps] / t_CK.AVG[ps] }, where WR is the value programmed in the EMR.
15) Input waveform timing t_DH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the V_IH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the V_IL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between V_IL.DC.MAX and
V_IH.DC.MIN. See Figure 3.
16) t_DQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. t_JIT.PER, t_JIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
18) Input waveform timing t_DS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the V_IH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the V_IL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between V_il(DC)MAX and V_ih(DC)MIN. See
Figure 3.
19) If t_DS or t_DH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
21) t_HP is the minimum of the absolute half period of the actual input clock. t_HP is an input parameter but not an input specification parameter.
It is used in conjunction with t_QHS to derive the DRAM output timing t_QH. The value to be used for t_QH calculation is determined by the
following equation; t_HP = MIN (t_CH.ABS, t_CL.ABS), where, t_CH.ABS is the minimum of the actual instantaneous clock high time; t_CL.ABS is the
minimum of the actual instantaneous clock low time.
22) t_HZ and t_LZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (t_HZ), or begins driving (t_LZ) .
23) Input waveform timing is referenced from the input signal crossing at the V_IL.DC level for a rising signal and V_IH.DC for a falling signal applied
to the device under test. See Figure 4.
24) Input waveform timing is referenced from the input signal crossing at the V_IH.AC level for a rising signal and V_IL.AC for a falling signal applied
to the device under test. See Figure 4.
25) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. t_JIT.PER, t_JIT.CC,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
26) t_QH = t_HP – t_QHS, where: t_HP is the minimum of the absolute half period of the actual input clock; and t_QHS is the specification value under
the max column. {The less half-pulse width distortion present, the larger the t_QH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides t_HP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides t_QH of 975 ps minimum. 2) If the system
provides t_HP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides t_QH of 1080 ps minimum.
27) t_QHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual t_HP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
28) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
29) 0 °C≤ T_CASE ≤ 85 °C
30) 85 °C < T_CASE ≤ 95 °C
31) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
Rev. 1.22, 2007-06
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07042006-834B-Z31V