HYB25DC256163CE-4 Datasheet, PDF (5/29 Pages) Qimonda AG – 256-Mbit Double-Data-Rate SGRAM

Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
2
Chip Configuration
The chip configuration of a DDR SGRAM is listed by function in Table 3. The abbreviations used in the Pin#/Buffer# column
are explained in Table 4 and Table 5 respectively. The chip numbering for TSOP is depicted in Figure 1.
Ball#
Name
Clock Signals
45
CK
46
CK
44
CKE
Control Signals
23
RAS
22
CAS
21
WE
24
CS
Address Signals
26
BA0
27
BA1
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10
AP
41
A11
42
A12
NC
17
A13
NC
Pin
Type
Buffer
Type
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
I
SSTL
NC
—
I
SSTL
NC
—
Function
Clock Signal
Complementary Clock Signal
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Select
Bank Address Bus 2:0
Address Bus 11:0
TABLE 3
Chip Configuration
Address Signal 12
Note: Module based on 256 Mbit or larger dies
Note: Module based on 128 Mbit or smaller dies
Address Signal 13
Note: 1 Gbit based module
Note: Module based on 512 Mbit or smaller dies
Rev. 1.1, 2007-01
5
03292006-SR4U-HULB