HYB25DC256163CE-4 Datasheet, PDF (22/29 Pages) Qimonda AG – 256-Mbit Double-Data-Rate SGRAM

Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
Parameter
TABLE 18
I_DD Conditions
Symbol
Operating Current: one bank; active/ precharge; t_RC = t_RCMIN; t_CK = t_CKMIN;
I_DD0
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two
clock cycles.
Operating Current: one bank; active/read/precharge; Burst = 4;
I_DD1
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤V_ILMAX; t_CK = t_CKMIN
Precharge Floating Standby Current: CS ≥ V_IHMIN, all banks idle;
CKE ≥ V_IHMIN; t_CK = t_CKMIN, address and other control inputs changing once per clock cycle, V_IN = V_REF for DQ, DQS
and DM.
I_DD2P
I_DD2F
Precharge Quiet Standby Current: CS ≥ V_IHMIN, all banks idle; CKE ≥ V_IHMIN; t_CK = t_CKMIN, address and other
control inputs stable at ≥ V_IHMIN or ≤ V_ILMAX; V_IN=V_REF for DQ, DQS and DM.
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ V_ILMAX; t_CK= t_CKMIN; V_IN = V_REF for DQ, DQS and DM.
Active Standby Current: one bank active; CS ≥ V_IHMIN; CKE ≥ V_IHMIN; t_RC = t_RASMAX; t_CK = t_CKMIN; DQ, DM and DQS
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle
I_DD2Q
I_DD3P
I_DD3N
Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing
once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A,
CL = 3 for DDR333; t_CK = t_CKMIN; I_OUT = 0 mA
Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing
once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A,
CL = 3 for DDR333; t_CK = t_CKMIN
Auto-Refresh Current: t_RC = t_RFCMIN, burst refresh
Self-Refresh Current: CKE ≤ 0.2 V; external clock on; t_CK = t_CKMIN
Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for detailed test
conditions.
I_DD4R
I_DD4W
I_DD5
I_DD6
I_DD7
Rev. 1.1, 2007-01
22
03292006-SR4U-HULB