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HYB25DC256163CE-4 Datasheet, PDF (19/29 Pages) Qimonda AG – 256-Mbit Double-Data-Rate SGRAM
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Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
TABLE 16
AC Operating Conditions
Parameter
Symbol
Min.
Values
Max.
Unit Note/ Test
Condition
Input High (Logic 1) Voltage, DQ, DQS and DM Signals VIH(AC) VREF + 0.31
—
V
1)2)3)
Input Low (Logic 0) Voltage, DQ, DQS and DM Signals VIL(AC) —
VREF – 0.31
V
1)2)3)
Input Differential Voltage, CK and CK Inputs
VID(AC) 0.7
VDDQ + 0.6
V
1)2)3)4)
Input Closing Point Voltage, CK and CK Inputs
VIX(AC) 0.5 × VDDQ– 0.2 0.5 × VDDQ+ 0.2 V
1)2)3)5)
1) VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR200 - DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400); 0 °C ≤ TA ≤ 70 °C
2) Input slew rate = 1 V/ns.
3) Inputs are not recognized as valid until VREF stabilizes.
4) VID is the magnitude of the difference between the input level on CK and the input level on CK.
5) The value of VIX is expected to equal 0.5 × VDDQ of the transmitting device and must track variations in the DC level of the same.
Parameter
Symbol –4
DDR500
DQ output access tAC
time from CK/CK
CK high-level width tCH
Clock cycle time tCK
Min.
–0.6
0.45
4
CK low-level width tCL
Auto precharge
tDAL
write recovery +
precharge time
DQ and DM input tDH
hold time
DQ and DM input
pulse width (each
input)
tDIPW
DQS output access tDQSCK
time from CK/CK
DQS input low
(high) pulse width
(write cycle)
tDQSL,H
DQS-DQ skew
(DQS and
associated DQ
signals)
tDQSQ
0.45
28
0.4
1.75
–0.65
0.35
—
Max.
+0.6
–5
DDR400B
Min.
–0.65
TABLE 17
AC Timing - Absolute Specifications
–6
DDR333
Unit Note1)/ Test
Condition
Max. Min.
+0.65 –0.7
Max.
+0.7 ns 2)3)4)5)
0.55 0.45
12
5
0.55 0.45
—
35
0.55
12
0.55
—
0.45
0.55
6
12
0.45
0.55
(tWR/tCK)+(tRP/tCK)
tCK
2)3)4)5)
ns CL = 3.0
2)3)4)5)
tCK
2)3)4)5)
tCK
2)3)4)5)6)
—
0.4
—
1.75
—
0.45
—
1.75
—
ns
2)3)4)5)
—
ns
2)3)4)5)6)
+0.65 –0.65
—
0.35
+0.65 –0.6
—
0.35
+0.6 ns 2)3)4)5)
—
tCK
2)3)4)5)
0.5
—
0.5
—
0.45 ns TSOPII
2)3)4)5)
Rev. 1.1, 2007-01
19
03292006-SR4U-HULB
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