HYB25DC256163CE-4 Datasheet, PDF (24/29 Pages) Qimonda AG – 256-Mbit Double-Data-Rate SGRAM

Internet Data Sheet
HYB25DC256163CE
256-Mbit Double-Data-Rate SGRAM
4.3
Current Measurement Conditions
Legend: A = Activate, R = Read, P = Precharge, N = NOP
I_DD1: Operating Current: One Bank Operation, ACT- RD- PRE
1. General test condition
a) Only one bank is accessed with t_RC,MIN
b) Burst Mode, Address and Control inputs on NOP adge are changing once per clock cycle
c) 50% of data changing at every burst
d) I_OUT = 0 mA
2. Timing patterns
a) DDR333 (166 MHz, CL = 2.5): t_CK = 6 ns, BL = 4, t_RCD = 3 × t_CK, t_RC = 10 × t_CK, t_RAS = 7 × t_CK
Setup: A0 N N R0 N N N P0 N N
Read : A0 N N R0 N N N P0 N N - repeat the same timing with random address changing
b) DDR400A (200 MHz, CL = 2.5): t_CK = 5 ns, BL = 4, t_RCD = 3 × t_CK, t_RC = 11 × t_CK, t_RAS = 8 × t_CK
Setup: A0 N N R0 N N N N P0 N N
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
c) DDR500 (250 MHz, CL = 3): t_CK =4 ns, BL =4, t_RCD = 3 × t_CK, t_RC = 13 × t_CK, t_RAS = 10 × t_CK
Setup: A0 N N R0 N N N N N N P0 N N
Read : A0 N N R0 N N N N N N P0 N N - repeat the same timing with random address changing
I_DD7: Operating Current: Four Bank Operation
1. General test condition
a) Four banks are being interleaved with t_RCMIN
b) Burst Mode, Address and Control inputs on NOP edge are not changing
c) 50% of data changing at every burst
d) I_OUT = 0 mA
2. Timing patterns
a) DDR333 (166 MHz, CL = 2.5): t_CK = 6 ns, BL = 4, t_RRD = 2 × t_CK, t_RCD = 3 × t_CK, t_RAS = 7 × t_CK, t_RC = 10 × t_CK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with random address changing
b) DDR400A (200 MHz, CL = 2.5): t_CK = 5 ns, BL = 4, t_RRD = 2 × t_CK, t_RCD = 3 × t_CK, t_RAS = 8 × t_CK, t_RC = 11 × t_CK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N N
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N N - repeat the same timing with random address changing
c) DDR500 (250Mhz, CL=3): t_CK = 4 ns, BL=4, t_RRD = 2 × t_CK, t_RCD = 3 × t_CK , t_RAS = 10 × t_CK, t_RC = 13 × t_CK
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N N
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N N - repeat the same timing with random address changing
Rev. 1.1, 2007-01
24
03292006-SR4U-HULB