HYB18M1G320BF Datasheet, PDF (44/62 Pages) Qimonda AG – DRAMs for Mobile Applications 1-Gbit x32 DDR Mobile-RAM

Data Sheet
HY[B/E]18M1G320BF
1-Gbit DDR Mobile-RAM
CK
CK
CKE
Command
T0
T1
T2
Tn
NOP
CMD
Timing Condition
NOP
NOP
NOP
Clock
Stopped
Exit
Clock
Stop
Valid
Command
Enter
Clock
Stop
FIGURE 38
Clock Stop
= Don't Care
TABLE 16
Minimum Number of Required Clock Pulses per Access Command
Command
Timing Condition
- 7.5 Unit Note
ACTIVE
READ (Auto-Precharge Disabled)
READ (Auto-Precharge Enabled)
WRITE (Auto-Precharge Disabled)
WRITE (Auto-Precharge Enabled)
t_RCD
(BL / 2) + CL
[(BL / 2) + t_RP]; [(BL / 2) + CL]
1 + (BL / 2) + t_WR
1 + (BL / 2) + t_DAL
3
t_CK
1)
5
t_CK
1)2)
5
t_CK
1)2)3)
5
t_CK
1)2)
8
t_CK
1)2)
PRECHARGE
AUTO REFRESH
t_RP
t_RFC
3
t_CK
1)
10
t_CK
1)
MODE REGISTER SET
t_MRD
2
t_CK
1) These parameters depend on the operating frequency; the number of clock cycles shown are calculated for a clock frequency of 133 MHz
for -7.5.
2) The values apply for a burst length of 4 and a CAS latency of 3.
3) Both timing conditions need to be satisfied; if not equal, the larger value applies
2.4.12 Clock Frequency Change
Depending on system considerations, it might be desired to change the DDR Mobile-RAM’s clock frequency while the device
is powered up. The DDR Mobile-RAM supports a clock frequency change when the device is in:
• self refresh mode (see Figure 35);
• power-down mode (see Figure 37);
• clock stop mode (see Figure 38).
Once the clock runs stable at the new clock frequency, the timing conditions for exiting these states have to be met before
applying the next access command. It should be pointed out that a continuous frequency drift is not considered a stable clock
and therefore is not supported.
Rev.1.00, 2007-03
44
02022006-J7N7-GYFP