HYB18M1G320BF Datasheet, PDF (31/62 Pages) Qimonda AG – DRAMs for Mobile Applications 1-Gbit x32 DDR Mobile-RAM

Data Sheet
HY[B/E]18M1G320BF
1-Gbit DDR Mobile-RAM
Parameter
Symbol
- 7.5
Unit Note
min. max.
Write postamble
t_WPST
0.4 0.6
t_CK
7)
Write preamble
t_WPRE
0.25 –
t_CK
–
ACTIVE to PRECHARGE command period
t_RAS
45
70,000 ns
8)
ACTIVE to ACTIVE command period
t_RC
65
–
ns
8)
ACTIVE to READ or WRITE delay
t_RCD
22.5 –
ns
8)
WRITE recovery time
t_WR
15
–
ns
8)
Internal write to Read command delay
t_WTR
1
–
t_CK
–
PRECHARGE command period
t_RP
22.5 –
ns
8)
1) DQ, DM and DQS input slew rate is measured between V_ILD(DC) and V_IHD(AC) (rising) or V_IHD(DC) and V_ILD(AC) (falling).
2) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions
through the DC region must be monotonic.
3) Input slew rate ≥ 1.0 V/ns.
4) Input slew rate ≥ 0.5V/ns and < 1.0 V/ns.
5) This parameter guarantees device timing. It is verified by device characterization but are not subject to production test.
6) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on t_DQSS.
7) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) will degrade accordingly.
8) These parameters account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round to the next higher integer.
During WRITE bursts, the first valid data-in element is registered on the first rising edge of DQS following the WRITE command,
and subsequent data elements are registered on successive edges of DQS. The LOW state on DQS between the WRITE
command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is
known as the write postamble. The time between the WRITE command and the first corresponding rising edge of DQS (t_DQSS)
is specified with a relatively wide range (from 75% to 125% of a clock cycle). The diagrams in Figure 23 show the two extremes
of t_DQSS for a burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQs will remain
High-Z and any additional input data is ignored.
Rev.1.00, 2007-03
31
02022006-J7N7-GYFP