HYB18M1G320BF Datasheet, PDF (43/62 Pages) Qimonda AG – DRAMs for Mobile Applications 1-Gbit x32 DDR Mobile-RAM

Data Sheet
HY[B/E]18M1G320BF
1-Gbit DDR Mobile-RAM
Parameter
Exit power down delay
CKE minimum low time
Symbol
TABLE 15
Timing Parameters for POWER-DOWN
- 7.5
Unit Note
min.
max.
t_XP
t_CKE
t_CK + t_IS
–
2
–
ns
t_CK
–
2.4.10.1 DEEP POWER-DOWN
Deep Power-Down mode is a unique feature of DDR Mobile-RAMs for extremely low power consumption. Deep Power-Down
mode is entered using the BURST TERMINATE command (cf Table 6) except that CKE is LOW. All internal voltage generators
are stopped and all memory data is lost in this mode. To enter the Deep Power-Down mode all banks must be precharged.
The Deep Power-Down mode is asynchronously exited by asserting CKE HIGH. After the exit, the same command sequence
as for power-up initialization, including the 200µs initial pause, has to be applied before any other command may be issued (cf.
Figure 4).
2.4.11 CLOCK STOP
Stopping the clock during idle periods is a very effective method to reduce power consumption. The DDR Mobile-RAM supports
clock stop in case:
• the last access command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has
executed to completion, including any data-out during read bursts; the number of clock pulses per access command
depends on the device’s AC timing parameters and the clock frequency (see Table 16);
• the related timing condition (t_RCD, t_WR, t_RP, t_RFC, t_MRD) has been met;
• CKE is held HIGH.
When all conditions have been met, the device is either in “idle” or “row active” state (cf. Figure 4), and clock stop mode may
be entered with CK held LOW and CK held HIGH.
Clock stop mode is exited by restarting the clock. At least one NOP command has to be issued before the next access
command may be applied. Additional clock pulses might be required depending on the system characteristics.
Figure 38 illustrates the clock stop mode:
• initially the device is in clock stop mode;
• the clock is restarted with the rising edge of T0 and a NOP on the command inputs;
• with T1 a valid access command is latched; this command is followed by NOP commands in order to allow for clock stop as
soon as this access command has completed;
• Tn is the last clock pulse required by the access command latched with T1
• the timing condition of this access command is met with the completion of Tn; therefore Tn is the last clock pulse required
by this command and the clock is then stopped.
Rev.1.00, 2007-03
43
02022006-J7N7-GYFP