HYB18M1G320BF Datasheet, PDF (32/62 Pages) Qimonda AG – DRAMs for Mobile Applications 1-Gbit x32 DDR Mobile-RAM

Data Sheet
HY[B/E]18M1G320BF
1-Gbit DDR Mobile-RAM
CK
CK
Command
Address
DQS
DQ
DM
DQS
DQ
DM
WRITE
BA,Col b
t_DQSSmin
NOP
Di b
t_DQSSmax
Di b
NOP
FIGURE 23
WRITE Burst (min. and max. t_DQSS)
NOP
NOP
NOP
DI b = Data In to column b.
3 subsequent elements of Data In are applied in the programmed order following DI b.
A non-interrupted burst of 4 is shown.
A10 is LOW with the WRITE command (Auto Precharge is disabled)
= Don't Care
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a
continuous flow of input data can be maintained. The new WRITE command can be issued on any clock cycle following the
previous WRITE command. The first data element from the new burst is applied after either the last element of a completed
burst or the last desired data element of a longer burst which is being truncated. The new WRITE command should be issued
x clock cycles after the first WRITE command, where x equals the number of desired data element pairs (pairs are required by
the 2n pre fetch architecture).
Figure 24 shows concatenated WRITE bursts of 4.
Rev.1.00, 2007-03
32
02022006-J7N7-GYFP