SAA7391 Datasheet, PDF (94/108 Pages) NXP Semiconductors – ATAPI CD-R block encoder/decoder

Philips Semiconductors
ATAPI CD-R block encoder/decoder
11.4 UART timing
Objective specification
SAA7391
handbook, full pagewidth
idle
10 × period (80 to 320 µs)
01234567P
next start may be here
STOP
parity
data
START
MGK614
See Section 7.9 for relevant timing.
Fig.30 Timing diagram of byte transmission of UART in asynchronous mode.
handbook, fu_Sll _Ppa_Ig_Ae_Cwi_Kdth
txfull
rxfull
SPI clock
SerIn, SerOut
'erln' samples
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
MGK615
See Section 7.9 for relevant timing.
Fig.31 Timing diagram of SPI mode, byte transmission of UART in synchronous mode.
1997 Aug 01
94