SAA7391 Datasheet, PDF (50/108 Pages) NXP Semiconductors – ATAPI CD-R block encoder/decoder

Philips Semiconductors
ATAPI CD-R block encoder/decoder
Objective specification
SAA7391
7.5.6.2 Auxiliary block memory processor registers
The registers given in Table 85 are located in the Aux
block of the and control the SAA7391 memory processor
buffer management. Transfer to/from the host is possible
as soon as the HOSTBYTECOUNT is non-zero, and the
HOSTCURSEGCNT is non-zero.
The ‘chan0’ and ‘chan1’ bits control the sequencing of
sub-block transfers. They indicate the number of
offset/length pairs to use for each block being transferred.
Normally only channels 0 and 1 are needed for Mode 2
host transfers. Channels 2 and 3 are available for special
READ-CD command options.
An interrupt is associated with HOSTBYTECOUNT
becoming zero. This is an indication to the microcontroller
to reload the HOSTCURSEG and HOSTBYTECOUNT
registers for the next transfer.
The HOSTCURSEG, HOSTBYTEOFFSET and
HOSTBYTECOUNT registers indicate the address of the
next byte to be transferred to or from the host, in order that
the status of the interface may be read. The operation of
the HOSTBYTECOUNT and HOSTBYTEOFFSET
registers is given in Table 85.
Table 85 Host interface DMA pointers
ADDR
FF45H
FF44H
FF66H
FF59H
FF58H
FF5DH
FF5CH
FF51H
FF50H
FF55H
FF54H
FF5BH
FF5AH
FF5FH
FF5EH
FF53H
FF52H
FF57H
FF56H
FF43H
FF42H
FF65H
FF64H
FF69H
FF68H
FF6BH
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
NAME
HOSTCURSEG-L
HOSTCURSEG-H
HOSTCURSEGCNT
HOSTSUBBLKOFFSET0-L
HOSTSUBBLKOFFSET0-H
HOSTSUBBLKOFFSET1-L
HOSTSUBBLKOFFSET1-H
HOSTSUBBLKOFFSET2-L
HOSTSUBBLKOFFSET2-H
HOSTNEXTSEG-L
HOSTNEXTSEG-H
HOSTSUBBLKCOUNT0-L
HOSTSUBBLKCOUNT0-H
HOSTSUBBLKCOUNT1-L
HOSTSUBBLKCOUNT1-H
HOSTSUBBLKCOUNT2-L
HOSTSUBBLKCOUNT2-H
HOSTNEXTSEGCOUNT
HOSTRELOADFLAGS
HOSTBYTEOFFSET-L
HOSTBYTEOFFSET-H
HOSTBYTECOUNT-L
HOSTBYTECOUNT-H
HOSTRELSEG-L
HOSTRELSEG-H
AUX_FORM_SCAN
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
s7
s6 s5 s4 s3 s2 s1 s0
chan1 chan0 − s12 s11 s10 s9 s8
b7
b6 b5 b4 b3 b2 b1 b0
a7
a6 a5 a4 a3 a2 a1 a0
autoform form −
− a11 a10 a9 a8
a7
a6 a5 a4 a3 a2 a1 a0
autoform form −
− a11 a10 a9 a8
a7
a6 a5 a4 a3 a2 a1 a0
autoform form −
− a11 a10 a9 a8
a7
a6 a5 a4 a3 a2 a1 a0
autoform form − a12 a11 a10 a9 a8
c7
c6 c5 c4 c3 c2 c1 c0
−
−
−
− c11 c10 c9 c8
c7
c6 c5 c4 c3 c2 c1 c0
−
−
−
− c11 c10 c9 c8
c7
c6 c5 c4 c3 c2 c1 c0
−
−
−
− c11 c10 c9 c8
c7
c6 c5 c4 c3 c2 c1 c0
rel1 rel2 −
− c11 c10 c9 c8
a7
a6 a5 a4 a3 a2 a1 a0
autoform form −
− a11 a10 a9 a8
c7
c6 c5 c4 c3 c2 c1 c0
−
−
−
− c11 c10 c9 c8
s7
s6 s5 s4 s3 s2 s1 s0
chan1 chan0 − s12 s11 s10 s9 s8
c7
c6 c5 c4 c3 c2 c1 c0
1997 Aug 01
50