SAA7391 Datasheet, PDF (35/108 Pages) NXP Semiconductors – ATAPI CD-R block encoder/decoder

Philips Semiconductors
ATAPI CD-R block encoder/decoder
Objective specification
SAA7391
• Reduces microcontroller load in simple streaming
transfers to or from host using a circular buffer
• Recognizes ATA SRST, the ATAPI reset command
(0X08) and the ATAPI packet command (0XA0) and
handles these automatically in ATAPI mode
• Handles unexpected ATA commands during PIO data
transfers
• Provides automatic DRQ for all PIO data transfers
• Provides automatic detection of ATAPI packet (A0)
command and reception of the packet bytes
• Provides automatic completion sequence for PIO DMA
and ultra DMA transfers
• Supports shadowing of registers for single drive
configurations with non-existent slave.
7.5.2 DESCRIPTION OF THE HOST INTERFACE BLOCK
The host interface block consists of three FIFOs which can
be configured by the DTCTR register to generate the
required data path through the host interface block. The
design supports ATAPI (revision 2.6) for CD-ROM
interfaces.
The host interface has a shadow status register to permit
proper ATA operation. The PDIAG and DASP signals are
controlled by the register bits in the host interface block.
The microcontroller has access to all registers in the host
interface block. The microcontroller can control all
operations required for data transfer to and from the host,
but may configure the host interface sequencer to
automate the following three operations:
1. Automation of detection of the A0 packet command
and reception of the 12-byte packet.
2. Automation of the data transfer sequences for PIO,
DMA and ultra DMA modes of data transfer.
3. Automation of completion sequences for PIO, DMA
and ultra DMA modes of data transfer.
The host interface provides a generic interface mode for a
glueless connection to an external SCSI controller device.
In this mode the microcontroller can configure the registers
of the SCSI controller device and initiate DMA transfers.
7.5.2.1 The SAA7391 host interface ATAPI registers visible to the host
Table 55 Host interface registers as seen from the host (note 1)
CS0 CS1 DA2 DA1 DA0
HOST READ (DIOR)
HOST WRITE (DIOW)
1
0
1
1
0
ALT STATUS: alternative status ADCTRL: ATAPI device control
1
0
1
1
1
0
1
0
0
0
ADRADR: ATAPI drive address
DATA: data register
not used
DATA: data register
0
1
0
0
1
AERR: ATAPI error register
AFEAT: ATAPI features register
0
1
0
0
1 SHERR: ATAPI error register (shadow) unused
0
1
0
1
0 AINTR: ATAPI interrupt reason register unused
0
1
0
1
1
ASAMT: ATAPI SAM TAG register ASAMT: ATAPI SAM TAG register
0
1
1
0
0
DBCL: ATAPI byte count low
DBCL: ATAPI byte count low
0
1
1
0
1
DBCH: ATAPI byte count high
DBCH: ATAPI byte count high
0
1
1
1
0 ADRSEL: ATAPI drive select register ADRSEL: ATAPI drive select register
0
1
1
1
1
ASTAT: ATAPI status register
ACMD: ATAPI command register
0
1
1
1
1
SHSTAT: ATAPI status register
(shadow)
unused
Note
1. The operation of these registers complies with the ATA-3 specification (revision 6) and the ATAPI specification
(revision 2.6).
1997 Aug 01
35