SAA7391 Datasheet, PDF (32/108 Pages) NXP Semiconductors – ATAPI CD-R block encoder/decoder

Philips Semiconductors
ATAPI CD-R block encoder/decoder
Objective specification
SAA7391
7.4 Interrupt registers
The interrupt system in the SAA7391 is intended to make it possible to acknowledge interrupts both independently
without interference or together. There are two interrupt pins to the sub-CPU from the SAA7391. The INT pin is
associated only with the host interface register IFSTAT (address FF92H). The INT2 pin is associated with 6 interrupt
registers which cover the SAA7391 drive block and UART. Two status/reset registers and two interrupt enable register
for the drive block and one status/reset register plus an interrupt enable register for the UART.
Table 44 IFSTAT interrupt register for the host interface; address FF92H (note 1)
ACCESS
R
BIT 7
cmdi
BIT 6
dtei
BIT 5
drqi
BIT 4
ultra_stop
BIT 3
dtbsy
BIT 2
srsti
Note
1. Interrupt status bits are described in the host interface; see Section 7.5.3.18.
BIT 1
reset08
BIT 0
a0comp/
crc_error
7.4.1 INTERRUPT 1
By writing a logic 1 to the INT1RESET register the bits will negate the INT1STATUS register bits. Writing a logic 1 to an
INT1ENABLE bit will enable the corresponding status bit. Writing a logic 0 will disable the status to zero.
Table 45 INT1STATUS: drive interrupt register status; address FF7AH (see Table 54)
ACCESS
R
BIT 7
dec
BIT 6
nocor
BIT 5
erablk
BIT 4
cblk
BIT 3
uceblk
BIT 2
crc-ng
BIT 1
q-ng
BIT 0
int2
Table 46 INT1RESET: drive interrupt register reset; address FF7AH (see Table 54)
ACCESS
W
BIT 7
dec
BIT 6
nocor
BIT 5
erablk
BIT 4
cblk
BIT 3
uceblk
BIT 2
crc-ng
BIT 1
q-ng
BIT 0
−
7.4.1.1 INT1ENABLE: drive interrupt register enable bits
Table 47 INT1ENABLE: drive interrupt register enable; address FF7BH (see Table 54)
ACCESS
W
BIT 7
dec
BIT 6
nocor
BIT 5
erablk
BIT 4
cblk
BIT 3
uceblk
BIT 2
crc-ng
BIT 1
q-ng
BIT 0
int2
1997 Aug 01
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