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SAA7391 Datasheet, PDF (70/108 Pages) NXP Semiconductors – ATAPI CD-R block encoder/decoder
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Philips Semiconductors
ATAPI CD-R block encoder/decoder
Objective specification
SAA7391
11 TIMING CHARACTERISTICS
11.1 External memory interface timing
Table 104 DRAM interface timing (fast-page mode); see Figs 13 and 14 and note 1
SYMBOL
Tcy
tACC(CAS)
tACC(RAS)
tRASH
tRASL
th(RAS)
tCASL
th(CAS)
td(CASH-RAS)
td(RAS-CAS)
td(RAS-CA)
tsu(RA)
th(RA)
tsu(CA)
th(CA)
th(CA-RASL)
tl(CA-RAS)
th(R)
th(R-RAS)
tsu(W)
th(W)
tWL
th(W-RAS)
tl(W-CAS)
tl(W-RAS)
tsu(DO)
th(DO)
th(DO-RAS)
PARAMETER
read or write cycle period
access time from CAS
access time from RAS
RAS HIGH time
RAS LOW time
RAS hold time
CAS LOW time
CAS hold time
delay time CAS HIGH to RAS
RAS to CAS delay time
RAS to column address delay time
row address set-up time
row address hold time
column address set-up time
column address hold time
column address hold time from RAS LOW
column address to RAS lead time
read command hold time
read command hold time from RAS
write command set-up time
write command hold time
write command LOW time
write command hold time from RAS
write command to CAS lead time
write command to RAS lead time
data output set-up time
data output hold time
data output hold time from RAS
CONDITIONS
MIN.
160
−
−
70
80
20
20
80
10
25
20
0
15
0
20
60
40
0
60
0
15
15
60
20
20
0
15
60
MAX.
−
20
−
−
10 000
−
10 000
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1. For further information regarding the DRAM timing please consult the device user manual or contact product support.
1997 Aug 01
70
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