SAA7391 Datasheet, PDF (83/108 Pages) NXP Semiconductors – ATAPI CD-R block encoder/decoder

Philips Semiconductors
ATAPI CD-R block encoder/decoder
Objective specification
SAA7391
11.2.3 ULTRA DMA OPERATION AND TIMING
Selection of ultra DMA is similar to multi-word DMA operation. Bits 5, 6 and 7 of the DTCTR register should all be set to
logic 1 and data byte counts and data flow selection does not change from ATAPI DMA operation.
The ‘ultra_stop’ interrupt (IFSTAT bit 4) when enabled by ‘ultra_stopien’ (IFCTRL bit 4) will interrupt the microcontroller
if the host stops a transfer before the required data has been transfer i.e. the data byte count has not reached zero.
A flag, ‘crc_error’ (IFSTAT bit 0) if asserted in conjunction with the ‘dtei’ interrupt (IFSTAT bit 6) will indicate to the
microcontroller that the last transfer of data was corrupt.
No changes of pin direction are required for ultra DMA, but the ATA description changes (see Table 109).
Table 109 Ultra DMA pin changes
ATA PIN NAME ULTRA DMA READ PIN NAME ULTRA DMA WRITE PIN NAME
COMMENT
IORDY
sender strobe
D_DMARDY
(device DMA ready)
D_DMARDY can be used to
pause transmission
DMARQ
DMARQ
DMARQ
similar to ATAPI DMA
DMACK
DMACK
DMACK
similar to ATAPI DMA, but also
used at the end of transmission
for the CRC strobe
DIOR
STOP
sender strobe
stop can terminate the data
transfer before all bytes have
been transferred; this action will
generate a microcontroller
interrupt
DIOW
H_DMARDY (host DMA ready) STOP
H_DMARDY can be used by to
pause transmission
11.2.4 ULTRA DMA READ/WRITE TIMING
This section provides the timing diagrams for the ultra DMA protocol. The timing diagrams are shown in Figs 18 to 27.
The timing information is provided in Table 110.
Table 110 Timing parameter values; see Figs 18 to 27
SYMBOL
T_cy
t_su(D)(RX)
t_h(D)(RX)
t_su(DV)
PARAMETER
CONDITIONS MIN.
cycle time (from STROBE edge to STROBE
Mode 0
117
edge)
Mode 1
77
Mode 2
57
data set-up time (at receiver)
Mode 0
15
Mode 1
10
Mode 2
7
data hold time (at receiver)
Mode 0
3
Mode 1
3
Mode 2
3
data valid set-up time (at sender); time from data Mode 0
75
bus being valid until STROBE edge
Mode 1
48
Mode 2
38
MAX.
−
−
−
−
−
−
−
−
−
−
−
−
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1997 Aug 01
83