SAA7391 Datasheet, PDF (49/108 Pages) NXP Semiconductors – ATAPI CD-R block encoder/decoder

Philips Semiconductors
ATAPI CD-R block encoder/decoder
Objective specification
SAA7391
7.5.4 TRANSFER COUNTER
The transfer counter register defines the total transfer length to be transferred to or from the host. This register is loaded
by the microcontroller and decrements synchronously with the DBCH/DBCL registers. The remainder packet size can be
loaded from the transfer counter into DBCH or DBCL when the transfer counter value becomes less than the packet size
store.
Table 82 Transfer counter register
ADDRESS
FFA0H
FFA1H
FFA2H
FFA3H
ACCESS
RW
RW
RW
RW
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
byte count (bits 7 to 0)
byte count (bits 15 to 8)
byte count (bits 23 to 16)
byte count (bits 31 to 24)
BIT 1
BIT 0
7.5.5 PACKET SIZE STORE
The packet size store will be loaded from the DBCH or DBCL registers when the host writes to ACMD, provided the drive
is selected. It may also be updated by the microcontroller. The DBCH/DBCL registers will be auto loaded from the packet
size store on condition that the transfer counter contains an equal or greater value than that held in the packet size store.
Table 83 Packet size store
ADDRESS
FFA4H
FFA5H
ACCESS
RW
RW
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
byte count (bits 7 to 0)
byte count (bits 15 to 8)
BIT 2
BIT 1
BIT 0
7.5.6 SEQUENCER STATUS
7.5.6.1 Sequencer status
For debugging the auto sequencer a sequencer status register has been provided (address FF6AH). A suspend
sequence bit has been provided (‘hiseq’ bit 4; see Table 76), which if asserted (logic 1) will suspend the auto sequencer
operation at its present state. The suspended state may then be read from the sequencer state register. If the sequencer
state is a write to a host interface registers state, then the sequencer will perform the write operation after the suspend
sequencer bit is negated by the microcontroller.
Table 84 Sequencer status: address FFA6H (note 1)
ACCESS
R
BIT 7
−
BIT 6
−
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
sequencer state (bits 5 to 0)
BIT 0
Note
1. For an explanation of the sequence state number see the user guide. The user guide is available from product
support.
1997 Aug 01
49