SAA7715 Datasheet, PDF (9/36 Pages) NXP Semiconductors – Digital Signal Processor

Philips Semiconductors
Digital Signal Processor
Preliminary specification
SAA7715H
8 FUNCTIONAL DESCRIPTION
8.1 PLL division factors for different clock inputs
An on-chip PLL generates the clock for the DSP. The DSP runs at a selectable frequency of maximum 70 MHz. The clock
is generated with the PLL that uses the CLK_IN of the chip to generate the DSP clock. Table 2 gives the division factors
and the values of the DSP_TURBO and the DIV_CLK_IN bits that need to be set via I²C-bus (see Table 10).
Table 2 PLL division factor per clock input.
CLOCK INPUT (MHz)
8.192 (32 kHz × 256)
9.728 (38 kHz × 256)
11.2896 (44.1 kHz × 256)
12.288 (48 kHz × 256)
16.384 (32 kHz × 512)
18.432 (32 kHz × 576)
19.456 (38 kHz × 512)
24.576 (96 kHz × 256)
pll_div[4:0]
10H
09H
03H
00H
10H
0BH
09H
00H
N
DSP_TURBO
DIV_CLK_IN
DSP_CLOCK
(MHz)
272
1
0
69.632
227
1
0
69.008
198
1
0
69.854
181
1
0
69.504
272
1
1
69.632
244
1
1
68.544
227
1
1
69.008
181
1
1
69.504
The above table does NOT imply that the clock input is restricted to the values given in this table. The clock input is
restricted to be within the range of 8.192 to 12.228 MHz. For higher clock frequencies pin DIV_CLK_IN should be set to
logic 1 performing a divide by 2 of the CLK_IN signal and thereby doubling the CLK_IN frequency range that is allowed
(16.384 to 24.576 MHz).
8.2 The word select PLL
A second on-chip PLL generates a selectable multiple of the sample rate frequency supplied on the word select
pin IIS_WS (= IIS_WS1). The clock generated by this so called WS_PLL is available for the user at pin SYSCLK.
Tables 3 and 4 show the I²C-bus settings needed to generate the n × f_s clock. The memory map of the I²C-bus bits is
shown in Table 10.
Table 3 Word select input range selection
SAMPLE RATE OF f_s (kHz)
32 to 50
50 to 96
sel_loop_div[1:0]
01
00
Table 4 Selection of n × f_s clock at SYSCLK output
sel2
sel1
sel0
SYSCLK (n × IIS_WS1)
1
0
0
512
0
1
1
384
0
1
0
256
0
0
1
192
0
0
0
128
DUTY FACTOR
50% for 32 to 50 kHz input; 66%
for 50 to 96 kHz input
50%
50%
50%
50%
2001 May 07
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