SAA7715 Datasheet, PDF (13/36 Pages) NXP Semiconductors – Digital Signal Processor

Philips Semiconductors
Digital Signal Processor
Preliminary specification
SAA7715H
8.6 I²C-bus interface (pins SCL and SDA)
The I²C-bus format is described in “The I²C-bus and how
to use it”, order no. 9398 393 40011.
For the external control of the SAA7715 a fast I²C-bus is
implemented. This is a 400 kHz bus which is downward
compatible with the standard 100 kHz bus.
There are two different types of control instructions:
• Loading of the Program RAM (PRAM) with the required
DSP program
– Programming the coefficient RAM (YRAM)
– Instructions to control the DSP program.
• Selection of the digital serial input/output format to be
used, the DSP clock speed.
The detailed description of the I²C-bus and the description
of the different bits in the memory map is given in
Chapter 9.
8.7 Reset
The reset (pin DSP_RESET) is active LOW and needs an
external 22 kΩ pull-up resistor. Between this pin and the
V_SSI ground a capacitor of 1 µF should be connected to
allow a proper switch-on of the supply voltage. The
capacitor value is such that the chip is in reset as long as
the power supply is not stabilized. A more or less fixed
relationship between the DSP reset and the POM time
constant is obligatory. The voltage on pin POM determines
the current flowing in the DACs.
The reset sets all I²C-bus bits to their default value and it
restarts the DSP program.
8.8 Power-down mode
The Power-down mode switches off all activity on the chip.
The Power-down mode can be switched on and off using
pin POWERDOWN. This pin needs to be connected to
ground if not used. The following applies for the
Power-down mode:
• Power-down mode may only be switched on when there
is no I²C-bus activity to or from the SAA7715
• Power-down mode may not be switched on before the
complete chip has been reset (DSP_RESET
active LOW)
• The clock signal on pin CLK_IN should be running
during Power-down mode
• It is advised to set pin POM to logic 0 before switching
on the Power-down mode and set it back to logic 1 after
the chip actually returns from Power-down mode as
shown in Fig.4
• All on-chip registers and memories will keep their values
during Power-down mode
• Digital serial outputs are not muted, the last value is kept
on the output
• The SAA7715 will not ‘lock-up’ the I²C-bus during
Power-down mode (SDA line).
Figure 4 shows the time the chip actually is in Power-down
mode after switching on/off pin POWERDOWN.
handbook, full pagewidth
CLK_IN
POWERDOWN
device actually in
Power-down mode
tA
POM
tB
MGT828
t_A = 4 × (256/CLK_IN); 8.192 MHz < CLK_IN < 12.288 MHz.
t_A = 4 × (512/CLK_IN); 16.384 MHz < CLK_IN < 24.576 MHz.
t_B = 128 × (256/CLK_IN); 8.192 MHz < CLK_IN < 12.288 MHz.
t_B = 128 × (512/CLK_IN); 16.384 MHz < CLK_IN < 24.576 MHz.
Fig.4 Power-down mode.
2001 May 07
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