SAA7715 Datasheet, PDF (28/36 Pages) NXP Semiconductors – Digital Signal Processor

Philips Semiconductors
Digital Signal Processor
14 I²S-BUS TIMING
Preliminary specification
SAA7715H
handbook, full pagewidth
WS
BCK
DATA IN
RIGHT
tBCK(H)
tr
tf
th(WS)
td(D)
tsu(WS)
tBCK(L)
Tcy
LSB
MSB
LEFT
tsu(D)
th(D)
DATA OUT
LSB
MSB
MGM129
Fig.9 Timing of the digital audio data inputs and outputs.
Table 19 Timing digital serial audio inputs and outputs (see Fig.9)
SYMBOL
T_cy
t_r
t_f
t_BCK(H)
t_BCK(L)
t_su(D)
t_h(D)
t_d(D)
t_su(WS)
t_h(WS)
PARAMETER
bit clock cycle time
rise time
fall time
bit clock HIGH time
bit clock LOW time
data set-up time
data hold time
data delay time
word select set-up time
word select hold time
CONDITIONS
T_cy = 50 ns
T_cy = 50 ns
T_cy = 50 ns
T_cy = 50 ns
T_cy = 50 ns
T_cy = 50 ns
T_cy = 50 ns
T_cy = 50 ns
T_cy = 50 ns
MIN.
162
−
−
0.35T_cy
0.35T_cy
0.2T_cy
0.2T_cy
−
0.2T_cy
0.2T_cy
TYP.
−
−
−
−
−
−
−
−
−
−
MAX.
−
0.15T_cy
0.15T_cy
−
−
−
−
0.15T_cy
−
−
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2001 May 07
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