SAA7715 Datasheet, PDF (17/36 Pages) NXP Semiconductors – Digital Signal Processor

Philips Semiconductors
Digital Signal Processor
Preliminary specification
SAA7715H
9.7 I²C-bus memory map specification
The I²C-bus memory map contains all defined I²C-bus bits. The map is split up in two different sections: the hardware
memory registers and the RAM definitions. In Table 8 the preliminary memory map is depicted. The hardware registers
are memory map on the XRAM of DSP. Table 9 shows the detailed memory map of those locations. All locations are
acknowledged by the SAA7715 even if the user tries to write to a reserved space. The data in these sections will be lost.
Reading from these locations will result in undefined data words.
Table 8 I²C-bus memory map
ADDRESS
8000H to 87FFH
602FH
2000H to 25FFH
1000H to 01FFH
0FF2H to 0FF5H, 0FFBH
0000H to 09FFH
FUNCTION
DSP to PROM (not readable via
I²C-bus)
DSP and general control
DSP to PRAM
DSP to YRAM
I²C-bus register
DSP to XRAM
2k × 32 bits
SIZE
1 × 24 bits
1.5k × 32 bits
512 × 12 bits
1 × 24 bits
2.5k × 24 bits
Table 9 I²C-bus memory map overview
ADDRESS
DESCRIPTION
Hardware registers
0FFBH
0FF5H
0FF4H
0FF3H
0FF2H
DSP control
602FH
Selector register 1
SPDIF IN channel status register 1 left
SPDIF IN channel status register 2 left
SPDIF IN channel status register 1 right
SPDIF IN channel status register 2 right
DSP and general control register
2001 May 07
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