SAA7715 Datasheet, PDF (29/36 Pages) NXP Semiconductors – Digital Signal Processor

Philips Semiconductors
Digital Signal Processor
15 I²C-BUS TIMING
Preliminary specification
SAA7715H
handbook, full pagewidth
SDA
tf
tLOW
tr
tSU;DAT
tf
tHD;STA
SCL
S
tHD;STA
tHD;DAT
tHIGH
tSU;STA
Sr
tSP
tr
tBUF
tSU;STO
P
S
MSC610
Fig.10 Definition of timing on the I²C-bus.
Table 20 Timing of I²C-bus (see Fig.10)
SYMBOL
f_SCL
t_BUF
t_HD;STA
t_LOW
t_HIGH
t_SU;STA
t_HD;DAT
t_SU;DAT
t_r
t_f
t_SU;STO
C_b
t_SP
PARAMETER
SCL clock frequency
bus free time between a
STOP and START
condition
hold time (repeated)
START condition; after this
period, the first clock pulse
is generated
SCL LOW period
SCL HIGH period
set-up time for a repeated
START condition
DATA hold time
DATA set-up time
rise time of both SDA and
SCL signals
fall time of both SDA and
SCL signals
set-up time for STOP
condition
capacitive load for each
bus line
pulse width of spikes to be
suppressed by input filter
CONDITIONS
C_b in pF
C_b in pF
STANDARD MODE
I²C-BUS
FAST MODE I²C-BUS
UNIT
MIN. MAX.
MIN.
MAX.
0
100
0
400
kHz
4.7
−
1.3
−
µs
4.0
−
0.6
−
µs
4.7
−
1.3
−
µs
4.0
−
0.6
−
µs
4.7
−
0.6
−
µs
0
−
0
0.9
µs
250
−
100
−
ns
−
1 000
20 + 0.1C_b 300
ns
−
300
20 + 0.1C_b 300
ns
4.0
−
0.6
−
µs
−
400
−
400
pF
not applicable
0
50
ns
2001 May 07
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