SAA7715 Datasheet, PDF (18/36 Pages) NXP Semiconductors – Digital Signal Processor

Philips Semiconductors
Digital Signal Processor
Preliminary specification
SAA7715H
9.8 I²C-bus memory map definition
Table 10 DSP and general control register (602FH)
NAME
pll_div[4:0]
dsp_turbo
pc_reset_dsp
sel[2:0]
sel_loop_div[1:0]
sel_FSDAC_clk
dis_SYSCLK
256f_s_n*Fs
SIZE
(BITS)
DESCRIPTION
1 reserved
5 PLL clock division factor according to Table 2
1 PLL output frequency
1: double
0: no doubling
1 reserved
1 program counter reset DSP
1: reset on
0: reset off
2 reserved
3 selection of n × f_s clock at SYSCLK output according to
Table 4
2 word select input range selection for WS_PLL according
to Table 3
2 reserved
2 clock source for FSDAC
00: WS_PLL if no signal to pin CLK_IN
01: 512f_s to pin CLK_IN
11: 256f_s to pin CLK_IN
1 output on pin SYSCLK
1: disable
0: enable
1 signal on pin SYSCLK
1: fixed 256f_s clock
0: n × f_s clock; determined by bits 13 to 11
1 reserved
DEFAULT
0
00011
1
BIT
POSITION
0
5 to 1
6
1
7
0
8
00
10 to 9
010
13 to 11
01
15 to 14
00
17 to 16
00
19 to 18
0
20
0
21
0
23 to 22
Table 11 SPDIF IN channel status register 2 right (0FF2H)
NAME
ch_stat_in right lsb
SIZE
(BITS)
DESCRIPTION
20 channel status SPDIF in right LSB bits 19 to 0
DEFAULT
00000H
BIT
POSITION
19 to 0
Table 12 SPDIF IN channel status register 1 right (0FF3H)
NAME
SIZE
(BITS)
DESCRIPTION
ch_stat_in right msb 20 channel status SPDIF in right MSB bits 39 to 20
DEFAULT
00000H
BIT
POSITION
19 to 0
2001 May 07
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