TDA4857PS Datasheet, PDF (8/56 Pages) NXP Semiconductors – I2C-bus autosync deflection controller for PC monitors

Philips Semiconductors
I²C-bus autosync deflection controller for
PC monitors
Product specification
TDA4857PS
The resistor R_HBUFpar is calculated as the value of R_HREF
and R_HBUF in parallel. The formulae for R_HBUF also takes
into account the voltage swing across this resistor
R_HBUF = ^R-R----HH---^RR----^EE---^FF----^×_–-----RR----_HH---_B-^B--_U-^U---_FF--_p-^p--_aa---_rr × 0.8 = 805 Ω
PLL1 phase detector
The phase detector is a standard type using switched
current sources, which are independent of the horizontal
frequency. It compares the middle of the horizontal sync
with a fixed point on the oscillator sawtooth voltage.
The PLL1 loop filter is connected to HPLL1 (pin 26).
See also Section “Horizontal position adjustment and
corrections”.
Horizontal position adjustment and corrections
A linear adjustment of the relative phase between the
horizontal sync and the oscillator sawtooth (in PLL1 loop)
is achieved via register HPOS. Once adjusted, the relative
phase remains constant over the whole frequency range.
Correction of pin unbalance and parallelogram is achieved
by modulating the phase between the oscillator sawtooth
and horizontal flyback (in loop PLL2) via registers
HPARAL and HPINBAL. If those asymmetric EW
corrections are performed in the deflection stage, both
registers can be disconnected from the horizontal phase
via control bit ACD. This does not change the output at
pin ASCOR.
Horizontal moire cancellation
To achieve a cancellation of horizontal moire (also known
as ‘video moire’), the horizontal frequency is
divided-by-two to achieve a modulation of the horizontal
phase via PLL2. The amplitude is controlled by register
HMOIRE. To avoid a visible structure on screen the
polarity changes with half of the vertical frequency. Control
bit MOD disables the moire cancellation function.
PLL2 phase detector
The PLL2 phase detector is similar to the PLL1 detector
and compares the line flyback pulse at HFLB (pin 1) with
the oscillator sawtooth voltage. The control currents are
independent of the horizontal frequency. The PLL2
detector thus compensates for the delay in the external
horizontal deflection circuit by adjusting the phase of the
HDRV (pin 8) output pulse.
For the TDA4857PS external modulation of the PLL2
phase is not allowed, because this would disturb the start
advance of the horizontal focus parabola.
Soft start and standby
If HPLL2 is pulled to ground by resetting the register
SOFTST, the horizontal output pulses, vertical output
currents and B+ control driver pulses will be inhibited. This
means that HDRV (pin 8), BDRV (pin 6), VOUT1 (pin 13)
and VOUT2 (pin 12) are floating in this state. If HPLL2 is
pulled to ground by an external DC current, vertical output
currents stay active while HDRV (pin 8) and BDRV (pin 6)
are in floating state. In both cases the PLL2 and the
frequency-locked loop are disabled, CLBL (pin 16)
provides a continuous blanking signal and HUNLOCK
(pin 17) is floating.
This option can be used for soft start, protection and
power-down modes. When the HPLL2 pin is released
again, an automatic soft start sequence on the horizontal
drive as well as on the B+ drive output will be performed
(see Figs 24 and 25).
A soft start can only be performed if the supply voltage for
the IC is a minimum of 8.6 V.
The soft start timing is determined by the filter capacitor at
HPLL2 (pin 30), which is charged with a constant current
during soft start. If the voltage at pin 30 (HPLL2) reaches
1.1 V, the vertical output currents are enabled. At 1.7 V the
horizontal driver stage generates very small output pulses.
The width of these pulses increases with the voltage at
HPLL2 until the final duty cycle is reached. The voltage at
HPLL2 increases further and performs a soft start at BDRV
(pin 6) as well. The voltage at HPLL2 continues to rise until
HPLL2 enters its normal operating range. The internal
charge current is now disabled. Finally PLL2 and the
frequency-locked loop are activated. If both functions
reach normal operation, HUNLOCK (pin 17) switches from
the floating status to normal vertical blanking, and
continuous blanking at CLBL (pin 16) is removed.
Output stage for line drive pulses [HDRV (pin 8)]
An open-collector output stage allows direct drive of an
inverting driver transistor because of a low saturation
voltage of 0.3 V at 20 mA. To protect the line deflection
transistor, the output stage is disabled (floating) for a low
supply voltage at V_CC (see Fig.23).
The duty cycle of line drive pulses is slightly dependent on
the actual horizontal frequency. This ensures optimum
drive conditions over the whole frequency range.
2000 Jan 31
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