TDA4857PS Datasheet, PDF (10/56 Pages) NXP Semiconductors – I2C-bus autosync deflection controller for PC monitors

Philips Semiconductors
I²C-bus autosync deflection controller for
PC monitors
Product specification
TDA4857PS
Adjustment of vertical position, vertical linearity and
vertical linearity balance
Register VPOS provides a DC shift at the sawtooth
outputs VOUT1 and VOUT2 (pins 13 and 12) and the EW
drive output EWDRV (pin 11) in such a way that the whole
picture moves vertically while maintaining the correct
geometry.
Register VLIN is used to adjust the amount of vertical
S-correction in the output signal. This function can be
switched off by control bit VSC.
Register VLINBAL is used to correct the unbalance of the
vertical S-correction in the output signal. This function can
be switched off by control bit VLC.
Adjustment of vertical moire cancellation
To achieve a cancellation of vertical moire (also known as
‘scan moire’) the vertical picture position can be modulated
by half the vertical frequency. The amplitude of the
modulation is controlled by register VMOIRE and can be
switched off via control bit MOD.
Horizontal pincushion (including horizontal size,
corner correction and trapezium correction)
EWDRV (pin 11) provides a complete EW drive waveform.
The components horizontal pincushion, horizontal size,
corner correction and trapezium correction are controlled
by the registers HPIN, HSIZE, HCOR and HTRAP.
HTRAP can be set to zero by control bit VPC.
The pincushion (EW parabola) amplitude, corner and
trapezium correction track with the vertical picture size
(VSIZE) and also with the adjustment for vertical picture
position (VPOS). The corner correction does not track with
the horizontal pincushion (HPIN).
Further the horizontal pincushion amplitude, corner and
trapezium correction track with the horizontal picture size,
which is adjusted via register HSIZE and the analog
modulation input HSMOD.
If the DC component in the EWDRV output signal is
increased via HSIZE or I_HSMOD, the pincushion, corner and
trapezium component of the EWDRV output will be
reduced by a factor of
1
–
V_HSIZE
+
V_HEHT


1
–
V-1---4-_{H--.-S-4--I-Z--V-E- }
-------------------------------1----4---.--4---------------------------------
The value 14.4 V is a virtual voltage for calculation only.
The output pin can not reach this value, but the gain (and
DC bias) of the external application should be such that the
horizontal deflection is reduced to zero when EWDRV
reaches 14.4 V.
HSMOD can be used for a DC controlled EHT
compensation by correcting horizontal size, horizontal
pincushion, corner and trapezium. The control range at
this pin tracks with the actual value of HSIZE. For an
increasing DC component V_HSIZE in the EWDRV output
signal, the DC component V_HEHT caused by I_HSMOD will be
reduced by a factor of 1 – ^V-1---4-H--.-^S-4--^I-^Z--V-^E- as shown in the previous
equation.
The whole EWDRV voltage is calculated as follows:
V_EWDRV = 1.2 V + [V_HSIZE + V_HEHT × f(HSIZE) + (V_HPIN +
V_HCOR + V_HTRAP) × g(HSIZE, HSMOD)] × h(I_HREF)
Where:
V_HEHT = _1-I--^H-2--^S-0--^M----_µ^O----A^D-- × 0.69
f(HSIZE) = 1 – -V1---4-^H--.-^S-4--^I-^Z--V-^E-
g(HSIZE, HSMOD)
=
1
–
V_HSIZE
+
V_HEHT


1
–
V-1---4-_{H--.-S-4--I-Z--V-E- }
-----------------------------1----4---.--4-----V-------------------------------
h(I_HREF) = _I--H----_R---_E-I--^HF---^R---_f^E--₌-^F--₇--₀--_k--_H--_z
Two different modes of operation can be chosen for the
EW output waveform via control bit FHMULT:
1. Mode 1
Horizontal size is controlled via register HSIZE and
causes a DC shift at the EWDRV output. The complete
waveform is also multiplied internally by a signal
proportional to the line frequency [which is detected
via the current at HREF (pin 28)]. This mode is to be
used for driving EW diode modulator stages which
require a voltage proportional to the line frequency.
2. Mode 2
The EW drive waveform does not track with the line
frequency. This mode is to be used for driving EW
modulators which require a voltage independent of the
line frequency.
2000 Jan 31
10