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TDA4857PS Datasheet, PDF (17/56 Pages) NXP Semiconductors – I2C-bus autosync deflection controller for PC monitors
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Philips Semiconductors
I2C-bus autosync deflection controller for
PC monitors
Product specification
TDA4857PS
SYMBOL
PARAMETER
CONDITIONS
MIN.
HPARAL
horizontal parallelogram
correction (referenced to
horizontal period)
register HPARAL = 0;
−
control bit HBC = 0; note 6
register HPARAL = 15; −
control bit HBC = 0; note 6
register HPARAL = X;
−
control bit HBC = 1; note 6
HMOIRE
relative modulation of
register HMOIRE = 0;
−
horizontal position by 0.5fH; control bit MOD = 0
phase alternates with 0.5fV
register HMOIRE = 31; −
control bit MOD = 0
HMOIREoff
moire cancellation off
control bit MOD = 1
−
PLL2 phase detector: pins HFLB and HPLL2
φPLL2
PLL2 control (advance of
maximum advance;
36
horizontal drive with respect to register HPINBAL = 07;
middle of horizontal flyback) register HPARAL = 07
minimum advance;
−
register HPINBAL = 07;
register HPARAL = 07
Ictrl(PLL2)
PLL2 control current
−
ΦPLL2
relative sensitivity of PLL2
−
phase shift related to
horizontal period
VPROT(PLL2)(max) maximum voltage for PLL2
−
protection mode/soft start
Ich(PLL2)
charge current for external
VHPLL2 < 3.7 V
−
capacitor during soft start
HORIZONTAL FLYBACK INPUT: PIN HFLB
Vpos(HFLB)
positive clamping voltage
IHFLB = 5 mA
−
Vneg(HFLB)
negative clamping voltage
IHFLB = −1 mA
−
Ipos(HFLB)
positive clamping current
−
Ineg(HFLB)
negative clamping current
−
Vsl(HFLB)
slicing level
−
Output stage for line driver pulses: pin HDRV
OPEN-COLLECTOR OUTPUT STAGE
Vsat(HDRV)
saturation voltage
IHDRV = 20 mA
−
IHDRV = 60 mA
−
ILO(HDRV)
output leakage current
VHDRV = 16 V
−
TYP.
−0.8
0.8
0
0
0.05
0
−
7
75
28
4.4
1
5.5
−0.75
−
−
2.8
−
−
−
MAX. UNIT
−
%
−
%
−
%
−
%
−
%
−
%
−
%
−
%
−
µA
−
mV/%
−
V
−
µA
−
V
−
V
6
mA
−2
mA
−
V
0.3
V
0.8
V
10
µA
2000 Jan 31
17
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