TDA4857PS Datasheet, PDF (12/56 Pages) NXP Semiconductors – I2C-bus autosync deflection controller for PC monitors

Philips Semiconductors
I²C-bus autosync deflection controller for
PC monitors
Product specification
TDA4857PS
• Buck converter in feed forward mode (see Fig.22)
This application uses an external RC combination at
BSENS to provide a pulse width which is independent
from the horizontal frequency. The capacitor is charged
via an external resistor and discharged by the internal
discharge circuit. For normal operation the discharge
circuit is activated when the flip-flop is reset by the
internal voltage comparator. The capacitor will now be
discharged with a constant current until the internally
controlled stop level V_STOP(BSENS) is reached. This level
will be maintained until the rising edge of the next HDRV
pulse sets the flip-flop again and disables the discharge
circuit.
If no reset is generated within a line period, the rising
edge of the next HDRV pulse automatically starts the
discharge sequence and resets the flip-flop. When the
voltage at BSENS reaches the threshold voltage
V_{RESTART(BSENS)}, the discharge circuit will be disabled
automatically and the flip-flop will be set immediately.
This behaviour allows a definition of the maximum duty
cycle of the B+ control drive pulse by the relationship of
charge current to discharge current.
Supply voltage stabilizer, references, start-up
procedures and protection functions
The TDA4857PS incorporates an internal supply voltage
stabilizer to provide excellent stabilization for all internal
references. An internal gap reference, especially designed
for low-noise, is the reference for the internal horizontal
and vertical supply voltages. All internal reference currents
and drive current for the vertical output stage are derived
from this voltage via external resistors.
If either the supply voltage is below 8.3 V or no data from
the I²C-bus has been received after power-up, the internal
soft start and protection functions do not allow any of those
outputs [HDRV, BDRV, VOUT1, VOUT2 and HUNLOCK
(see Fig.23)] to be active.
For supply voltages below 8.3 V the internal I²C-bus will
not generate an acknowledge and the IC is in standby
mode. This is because the internal protection circuit has
generated a reset signal for the soft start register SOFTST.
Above 8.3 V data is accepted and all registers can be
loaded. If register SOFTST has received a set from the
I²C-bus, the internal soft start procedure is released, which
activates all mentioned outputs.
If during normal operation the supply voltage has dropped
below 8.1 V, the protection mode is activated and
HUNLOCK (pin 17) changes to the protection status and is
floating. This can be detected by the microcontroller.
This protection mode has been implemented in order to
protect the deflection stages and the picture tube during
start-up, shut-down and fault conditions. This protection
mode can be activated as shown in Table 3.
Table 3 Activation of protection mode
ACTIVATION
Low supply voltage at
pin 10
Power dip, below 8.1 V
X-ray protection (pin 2)
triggered, XSEL (pin 9) is
open-circuit or connected
to ground
X-ray protection (pin 2)
triggered, XSEL (pin 9)
connected to V_CC via an
external resistor
HPLL2 (pin 30) externally
pulled to ground
RESET
increase supply voltage;
reload registers;
soft start via I²C-bus
reload registers;
soft start via I²C-bus
reload registers;
soft start via I²C-bus
switch V_CC off and on
again, reload registers;
soft start via I²C-bus
release pin 30
When the protection mode is active, several pins of the
TDA4857PS are forced into a defined state:
HDRV (horizontal driver output) is floating
BDRV (B+ control driver output) is floating
HUNLOCK (indicates, that the frequency-to-voltage
converter is out of lock) is floating (HIGH via external
pull-up resistor)
CLBL provides a continuous blanking signal
VOUT1 and VOUT2 (vertical outputs) are floating
The capacitor at HPLL2 is discharged.
If the soft start procedure is activated via the I²C-bus, all of
these actions will be performed in a well defined sequence
(see Figs 23 and 24).
2000 Jan 31
12