SAA7824 Datasheet, PDF (76/89 Pages) NXP Semiconductors – CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control (PhonIC)

Philips Semiconductors
CD audio decoder, digital servo and filterless
DAC with integrated pre-amp and laser control
Product specification
SAA7824
12 OPERATING CHARACTERISTICS (I²S-BUS TIMING)
V_DDD = 1.65 to 1.95 V; V_SS = 0 V; T_amb = 0 to 70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
I²S-bus timing (single speed × n); see Fig.35; note 1
CLOCK OUTPUT: PIN SCLK (C_L = 20 pF)
T_cy
output clock period
sample rate = f_s
sample rate = 2f_s
sample rate = 4f_s
t_CH
clock HIGH time
sample rate = f_s
sample rate = 2f_s
sample rate = 4f_s
t_CL
clock LOW time
sample rate = f_s
sample rate = 2f_s
sample rate = 4f_s
OUTPUTS: PINS WCLK, DATA AND EF (C_L = 20 pF)
t_su
set-up time
sample rate = f_s
sample rate = 2f_s
sample rate = 4f_s
t_h
hold time
sample rate = f_s
sample rate = 2f_s
sample rate = 4f_s
−
472.4/n −
ns
−
236.2/n −
ns
−
118.1/n −
ns
166/n −
−
ns
83/n
−
−
ns
42/n
−
−
ns
166/n −
−
ns
83/n
−
−
ns
42/n
−
−
ns
95/n
−
−
ns
48/n
−
−
ns
24/n
−
−
ns
95/n
−
−
ns
48/n
−
−
ns
24/n
−
−
ns
Note
1. In the normal operating mode the I²S-bus timing is directly related to the overspeed factor ‘n’. In the lock-to-disc mode
‘n’ is replaced by the disc speed factor ‘d’.
SCLK
WCLK
DATA
EF
2003 Oct 01
clock period Tcy
t _CL
t _CH
th
t _su
VDD – 0.8 V
0.8 V
VDD – 0.8 V
0.8 V
MBG407
Fig.35 I²S-bus timing diagram.
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