SAA7824 Datasheet, PDF (43/89 Pages) NXP Semiconductors – CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control (PhonIC)

Philips Semiconductors
CD audio decoder, digital servo and filterless
DAC with integrated pre-amp and laser control
Product specification
SAA7824
handbook, ful₍l_mpa_icg_re_ow^Sci^Id_oLt_nh^Dtroller)
SCL
(microcontroller)
SD
(SAA782X)
SILD
(microcontroller)
SD
(SAA782X)
SDA
(microcontroller)
D7 D6 D5 D4 D3 D2 D1 D0
data byte
microcontroller read (one data byte)
COMMAND
DATA1
DATA2
microcontroller read (full command)
DATA3
MBL450
Fig.33 Microcontroller protocol for read servo commands.
7.17.3 DECODER AND SHADOW REGISTERS
To maintain compatibility with the SAA732x series,
decoder registers 0 to F and the shadow registers are
largely unchanged. However, to control the extra
functionality of SAA7824, the shadow registers have been
extended to include new shadow registers.
All shadow registers are accessed by using the two LSBs
(bits 0 and 1) of decoder register F. These bits are called
SHADEN1 and SHADEN2 respectively. These bits are
decoded according to Table 15.
This two bit encoding allows the use of three shadow
register banks; bank 1 (SAA732X shadow registers), and
banks 2 and 3 (new shadow registers). Only the four
addresses 3, 7, A and C are implemented in any one
bank. Any other addresses sent while accessing any of the
shadow register banks are invalid and have no effect.
When SHADEN1 and SHADEN2 are both set to logic 0
(decoder register F set to XX00) all subsequent addresses
are decoded by the main decoder registers again.
Access to decoder register F is always enabled so that
SHADEN1 and SHADEN2 can be set or reset as required.
The SHADEN bits and subsequent shadow registers are
programmed identically to the main decoder registers,
i.e. they can be directly programmed when using the
SAA7824 in 4-wire mode or programmed via the servo
interface when using 3-wire or I²C-bus modes. The main
decoder registers are given in Table 16 and the shadow
registers in Table 18. Details of the new shadow registers
can be found in Tables 19 to 22.
2003 Oct 01
43