SAA7824 Datasheet, PDF (14/89 Pages) NXP Semiconductors – CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control (PhonIC)

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new shadow register 7 bank 2:
0XXX = pass all data
1XXX = pass correct data only
CD TEXT
INTERFACE
CDTRDY
CDTCLK
CDTDATA
1
V4
0
RCK
SUBCODE
PROCESSOR
output from
data slicer
DIGITAL PLL
AND
DEMODULATOR
FIFO
ERROR
CORRECTOR
0: register D = XX01
V4 SUBCODE
INTERFACE
CD GRAPHICS
INTERFACE
register F
SBSY
SFSY
SUB
MICROCONTROLLER
INTERFACE
SDA
Mute Bypass (Shadow Register 7 Bank 1)
Activate Mute (Decoder Reg 0)
1: decoder register A = XX0X
0: decoder register A = XX1X
Hard Mute (Decoder Reg C)
EBU
MUTE
EBU
INTERFACE
DOBM
decoder register A
1: shadow register 7 = XX1X
0: shadow register 7 = XX0X
FADE/MUTE/
INTERPOLATE
1
0
1: decoder register 3 = XX10
(1fs mode)
0: decoder register 3 ≠ XX10
1
PHASE
1
DIGITAL
0
COMPENSATION
0
FILTER
decoder register 3
INTERNAL
KILL
decoder register C
DE-EMPHASIS
FILTER
1
LKILL
loopback
0
RKILL
KILL
0: new shadow register A bank 2 = 0XX
1: new shadow register A bank 2 = 1XXX
1: no pre-emphasis detected
OR register D = 01XX
(de-emphasis signal at V5)
0: pre-emphasis detected
AND register D ≠ 01XX
1
0
1
0
I²S/EIAJ BUS
INTERFACE
SCLK
1
WCLK
0
DATA
EF
ONBOARD
DAC
DACRP
DACLP
DACRN
DACLN
1
0
decoder
register 3
1: shadow register 7 = XX1X
0: shadow register 7 = XX0X
I²S/EIAJ
LOOPBACK
INTERFACE
1: decoder register 3 ≠ 101X
0: decoder register 3 = 101X
(CD-ROM modes)
WCLI
SCLI
SDI
MDB501
Fig.8 Simplified data flow of decoder functions for the M1 version.