SAA7824 Datasheet, PDF (25/89 Pages) NXP Semiconductors – CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control (PhonIC)

Philips Semiconductors
CD audio decoder, digital servo and filterless
DAC with integrated pre-amp and laser control
Product specification
SAA7824
Table 11 Pin applications
PIN
NAME
V1
PIN
NUMBER
71
V2
72
V3
73
V4
74
V5
75
TYPE
input
input
output
output
output
REGISTER REGISTER
ADDRESS DATA
FUNCTION
1100
XXX1 external off-track signal input
−
XXX0 internal off-track signal used input may be read
via decoder status bit; selected via register 2
−
−
input may be read via decoder status bit;
selected via register 2
1100
00XX output = 0
−
01XX output = 1
1101
0000 4-line motor drive (using V4 and V5)
−
XX01 Q-to-W subcode output
−
XX10 output = 0
−
XX11 output = 1
1101
01XX de-emphasis output (active HIGH)
−
10XX output = 0
−
11XX output = 1
7.15 Spindle motor control
7.15.1 MOTOR OUTPUT MODES
The spindle motor speed is controlled by a fully integrated
digital servo. Address information from the internal ±8
frame FIFO and disc speed information are used to
calculate the motor control output signals. Several output
modes, selected by decoder register 6, are supported:
• Pulse density, 2-line (true complement output),
(1 × n) MHz sample frequency
• PWM output, 2-line, (22.05 × n) kHz modulation
frequency
• PWM output, 4-line, (22.05 × n) kHz modulation
frequency
• CDV motor mode.
7.15.1.1 Pulse density output mode
In the pulse density mode the motor output pin (MOTO1)
is the pulse density modulated motor output signal.
A 50% duty factor corresponds with the motor not
actuated, higher duty factors mean acceleration, lower
duty factors means braking. In this mode, the MOTO2
signal is the inverse of the MOTO1 signal. Both signals
change state only on the edges of a (1 × n) MHz internal
clock signal.
7.15.1.2 PWM output mode (2-line)
In the PWM mode the motor acceleration signal is put in
pulse-width modulation form on the MOTO1 output. The
motor braking signal is pulse-width modulated on the
MOTO2 output. The timing is illustrated in Fig 16. A typical
application diagram is illustrated in Fig 17.
2003 Oct 01
MOTO1
MOTO2
t _rep = 45 µs
tdead 240 ns
Accelerate
Brake
Fig.16 2-line PWM mode timing.
25
MGA366