PHN70308 Datasheet, PDF (7/10 Pages) NXP Semiconductors – N-channel enhancement mode TrenchMOS transistor array

Philips Semiconductors
N-channel enhancement mode
TrenchMOS transistor array
Product specification
PHN70308
Transconductance, gfs (S)
10
VDS > ID X RDS(ON)
9
Tj = 25 C
8
7
150 C
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10
Drain current, ID (A)
Fig.17. Typical transconductance (isolation FET)
T_j = 25 ˚C; g_fs = f(I_D)
Capacitances, Ciss, Coss, Crss (pF)
1000
Ciss
100
Coss
Crss
10
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Fig.18. Typical capacitances (spindle FET)
C = f(V_DS); conditions: V_GS = 0 V; f = 1 MHz
Capacitances, Ciss, Coss, Crss (pF)
10000
1000
Ciss
Coss
100
0.1
1
10
Drain-Source Voltage, VDS (V)
Crss
100
Fig.19. Typical capacitances (isolation FET)
C = f(V_DS); conditions: V_GS = 0 V; f = 1 MHz
Gate-source voltage, VGS (V)
15
14 ^{ID = 1A}
13 _{Tj = 25 C}
12
11 ^{VDD = 20 V}
10
9
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
Gate charge, QG (nC)
Fig.20. Typical turn-on gate-charge characteristics
(spindle FET); V_GS = f(Q_G)
Gate-source voltage, VGS (V)
15
14
13 _{ID = 1A}
12
11 ^{Tj = 25 C}
10 VDD = 20 V
9
8
7
6
5
4
3
2
1
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26
Gate charge, QG (nC)
Fig.21. Typical turn-on gate-charge characteristics
(isolation FET); V_GS = f(Q_G)
Source-Drain Diode Current, IF (A)
5
VGS = 0 V
4.5
4
3.5
3
2.5
150 C
2
1.5
Tj = 25 C
1
0.5
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Source-Drain Voltage, VSDS (V)
Fig.22. Typical reverse diode current (spindle FET)
I_F = f(V_SDS); conditions: V_GS = 0 V; parameter T_j
May 1999
7
Rev 1.000