PHN70308 Datasheet, PDF (4/10 Pages) NXP Semiconductors – N-channel enhancement mode TrenchMOS transistor array

Philips Semiconductors
N-channel enhancement mode
TrenchMOS transistor array
Product specification
PHN70308
SOURCE-DRAIN DIODE LIMITING VALUES AND CHARACTERISTICS
T_j = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
I_F
Continuous forward diode
T_sp = 50 ˚C
current
spindle FET; δ = 33.3% -
isolation FET -
I_FRM
Repetitive peak forward diode
current
spindle FET -
isolation FET -
V_F
Diode forward voltage
I_F = 1.25 A; V_GS = 0 V
spindle FET -
isolation FET -
t_rr
Reverse recovery time
I_F = 1.25 A; -dI_F/dt = 100 A/µs;
V_DS = 25 V
spindle FET -
isolation FET -
TYP.
-
-
-
-
0.8
0.8
20
25
MAX. UNIT
5
A
5
A
20
A
20
A
1
V
1
V
-
ns
-
ns
Normalised Power Derating, Ptot (%)
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80
100 120 140 160
Solder Point temperature, Tsp (C)
Fig.1. Normalised power dissipation.
PD% = 100⋅P_D/P_{D 25 ˚C} = f(T_sp)
Normalised Current Derating, ID (%)
120
100
80
60
40
20
0
0
20
40
60
80
100 120 140 160
Solder Point temperature, Tsp (C)
Fig.2. Normalised continuous drain current.
ID% = 100⋅I_D/I_{D 25 ˚C} = f(T_sp); conditions: V_GS ≥ 10 V
Normalised On-state Resistance
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
Fig.3. Normalised drain-source on-state resistance.
R_DS(ON)/R_{DS(ON)25 ˚C} = f(T_j)
Threshold Voltage, VGS(TO) (V)
3
2.75
2.5
2.25
2
1.75
typical
1.5
1.25
1
0.75
minimum
0.5
0.25
0
-60 -40 -20 0
20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
Fig.4. Gate threshold voltage.
V_GS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = V_GS
May 1999
4
Rev 1.000